AD7993 Analog Devices, AD7993 Datasheet - Page 28

• Manufacturer Part Number: AD7993
• Description: 4-Channel, 10-Bit ADC with I2C Compatible Interface in 16-Lead TSSOP
• Manufacturer: Analog Devices

Specifications of AD7993

• Resolution (bits): 10bit
• # Chan: 4
• Sample Rate: 188kSPS
• Interface: I²C/Ser 2-Wire,Ser
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: SOP

AD7993/AD7994
MODES OF OPERATION
When supplies are first applied to the AD7993/AD7994, the
ADC powers up in shutdown mode and normally remains in
this shutdown state while not converting. There are three
different methods of initiating a conversion on the devices.
MODE 1—USING THE CONVST PIN
A conversion can be initiated on the AD7993/AD7994 by
pulsing the CONVST signal. The conversion clock for the part
is internally generated so no external clock is required, except
when reading from or writing to the I
edge of CONVST , the AD7993/AD7994 begin to power up
(see Point A in Figure 32). The power-up time from shutdown
mode for the AD7993/AD7994 is approximately 1 µs; the
CONVST signal must remain high for 1 µs for the part to power
up fully. CONVST can be brought low after this time. The
falling edge of the CONVST signal places the track-and-hold
into hold mode; a conversion is also initiated at this point
(Point B in Figure 32). When the conversion is complete,
approximately 2 µs later, the parts return to shutdown (Point C
in Figure 32) and remain there until the next rising edge of
CONVST . The master can then read the ADC to obtain the
conversion result. The address pointer register must be pointing
to the conversion result register in order to read back the
conversion result.
CONVST
SCA
SDA
t
A
POWER-UP
B
t
CONVERT
C
S
1
2
C interface. On the rising
7-BIT ADDRESS
R
Figure 32. Mode 1 Operation
A
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9
1
FIRST DATA BYTE (MSBs)
If the CONVST pulse does not remain high for more than 1 µs,
the falling edge of CONVST still initiates a conversion but the
result is invalid because the AD7993/AD7994 are not fully
powered up when the conversion takes place. To maintain the
performance of the AD7993/AD7994 in this mode it is
recommended that the I
taking place.
The cycle timer register and Bits C4 to C1 in the address pointer
register should contain all 0s when operating the AD7994/
AD7993 in this mode. The CONVST pin should be tied low for
all other modes of operation. To select an analog input channel
for conversion in this mode, the user must write to the
configuration register and select the corresponding channel for
conversion. To set up a sequence of channels to be converted
with each CONVST pulse, set the corresponding channel bits in
the configuration register (see Table 11).
Once the conversion is complete, the master can address the
AD7993/AD7994 to read the conversion result. If further
conversions are required, the SCL line can be taken high while
the CONVST signal is pulsed again; then an additional 18 SCL
pulses are required to read the conversion result.
When operating the AD7993-1/AD7994-1 in Mode 1 and
reading after the conversion with a 3.4 MHz SCL, the ADCs can
achieve a throughput rate of up to 121 kSPS.
A
9
SECOND DATA BYTE (LSBs)
2
C bus is quiet when a conversion is
A
9
P