AD9481 Analog Devices, AD9481 Datasheet - Page 19

• Manufacturer Part Number: AD9481
• Description: 8-Bit, 250 MSPS, 3.3 V A/D Converter
• Manufacturer: Analog Devices

Specifications of AD9481

• Resolution (bits): 8bit
• # Chan: 1
• Sample Rate: 250MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p,1 V p-p
• Adc Architecture: Pipelined
• Pkg Type: QFP

External Reference
An external reference can be used for greater accuracy and
temperature stability when required. The gain of the AD9481
can also be varied using this configuration. A voltage output
DAC can be used to set VREF, providing for a means to digitally
adjust the full-scale voltage. VREF can be externally set to
voltages from 0.75 V to 1.5 V; optimum performance is typically
obtained at VREF = 1 V. (See the Typical Performance
Characteristics section.)
Programmable Reference
The programmable reference can be used to set a differential
input span anywhere between 0.75 V p-p and 1.5 V p-p by using
an external resistor divider. The SENSE pin self-biases to 0.5 V,
and the resulting VREF is equal to 0.5 × (1 + R1/R2). It is
recommended to keep the sum of R1 + R2 ≥ 10 kΩ to limit
VREF loading (for VREF = 1.5 V, set R1 equal to 7 kΩ and R2
equal to 3.5 kΩ).
CLOCKING THE AD9481
Any high speed ADC is extremely sensitive to the quality of the
sampling clock provided by the user. A track-and-hold circuit is
essentially a mixer, and any noise, distortion, or timing jitter on
the clock is combined with the desired signal at the A/D output.
Considerable care has been taken in the design of the CLOCK
input of the AD9481, and the user is advised to give
commensurate thought to the clock source.
The AD9481 has an internal clock duty cycle stabilization
circuit that locks to the rising edge of CLOCK and optimizes
timing internally for sample rates between 100 MSPS and
250 MSPS. This allows for a wide range of input duty cycles at
the input without degrading performance. Jitter on the rising
edge of the input is still of paramount concern and is not
reduced by the internal stabilization circuit. The duty cycle
control loop does not function for clock rates less than 70 MHz
nominally. The loop has a time constant associated with it that
needs to be considered in applications where the clock rate can
REFERENCE OR
10µF
DAC INPUT
EXTERNAL
Figure 36. Programmable Reference
Figure 35. External Reference
0.1µF
MAY REQUIRE
RC FILTER
AVDD
R1
R2
VREF
SENSE
VREF
SENSE
Rev. 0 | Page 19 of 28
change dynamically, requiring a wait time of 5 µs after a
dynamic clock frequency increase before valid data is available.
The clock duty cycle stabilizer can be disabled at Pin 28 (S1).
The clock inputs are internally biased to 1.5 V (nominal) and
support either differential or single-ended signals. For best
dynamic performance, a differential signal is recommended. An
MC100LVEL16 performs well in the circuit to drive the clock
inputs (ac coupling is optional). If the clock buffer is greater
than two inches from the ADC, a standard LVPECL
termination may be required instead of the simple pull-down
termination shown in Figure 37.
DS INPUTS
The data sync inputs (DS+, DS−) can be used in applications
which require that a given sample appear at a specific output
port (A or B) relative to a given external timing signal.
The DS inputs can also be used to synchronize two or more
ADCs in a system to maintain phasing between Ports A and B on
separate ADCs (in effect, synchronizing multiple DCO outputs).
The DS inputs are internally biased to 1.5 V (nominal) and
support either differential or single-ended signals. When DS+ is
held high (DS− low), the ADC data outputs and DCO outputs
do not switch and are held static. Synchronization is
accomplished by the assertion (falling edge) of DS+ within the
timing constraints t
(On initial synchronization, t
within the required setup time (t
edge N, the analog value at that point in time is digitized and
available at Port A, eight cycles later in interleaved mode. The
next sample, N + 1, is sampled by the next rising clock edge and
available at Port B, eight cycles after that clock edge.
Driving each ADC’s DS inputs by the same sync signal
accomplishes synchronization between multiple ADCs. In
applications which require synchronization, one-shot
synchronization is recommended. An easy way to accomplish
synchronization is by a one-time sync at power-on reset.
PECL
GATE
510kΩ
Figure 37. Clocking the AD9481
SDS
and t
HDS
HDS
, relative to a clock rising edge.
is not relevant.) If DS+ falls
SDS
510kΩ
) before a given clock rising
0.1µF
0.1µF
CLK+
CLK–
AD9481
AD9481