AD7440

Manufacturer Part NumberAD7440
DescriptionDifferential Input, 1 MSPS, 12- (AD7450A) & 10-Bit (AD7440) ADCs
ManufacturerAnalog Devices
AD7440 datasheet
 


Specifications of AD7440

Resolution (bits)10bit# Chan1
Sample Rate1MSPSInterfaceSer,SPI
Analog Input TypeDiff-UniAin Range(2Vref) p-p
Adc ArchitectureSARPkg TypeSOT
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FEATURES
Fast throughput rate: 1 MSPS
Specified for V
of 3 V and 5 V
DD
Low power at max throughput rate
4 mW max at 1 MSPS with 3 V supplies
9.25 mW max at 1 MSPS with 5 V supplies
Fully differential analog input
Wide input bandwidth
70 dB SINAD at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface
SPI®/QSPI™/MICROWIRE™/DSP compatible
Power-down mode: 1 μA max
8-lead SOT-23 and MSOP packages
APPLICATIONS
Transducer interface
Battery-powered systems
Data acquisition systems
Portable instrumentation
Motor control
GENERAL DESCRIPTION
1
The AD7440/AD7450A
are 10-bit and 12-bit high speed, low
power, successive approximation (SAR) analog-to-digital
converters with a fully differential analog input. These parts
operate from a single 3 V or 5 V power supply and use
advanced design techniques to achieve very low power
dissipation at throughput rates up to 1 MSPS. The SAR
architecture of these parts ensures that there are no pipeline
delays.
The parts contain a low noise, wide bandwidth, differential
track-and-hold amplifier (T/H) that can handle input
frequencies up to 3.5 MHz. The reference voltage is applied
externally to the V
pin and can be varied from 100 mV to
REF
3.5 V depending on the power supply and what suits the
application. The value of the reference voltage determines the
common-mode voltage range of the part. With this truly
differential input structure and variable reference input, the
user can select a variety of input ranges and bias points.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the device to interface
with microprocessors or DSPs. The input signals are sampled
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Differential Input, 1 MSPS
10-Bit and 12-Bit ADCs in an 8-Lead SOT-23
V
IN+
V
IN–
V
REF
AD7440/AD7450A
GND
on the falling edge of CS ; the conversion is also initiated at this
point. The SAR architecture of these parts ensures that there are
no pipeline delays. The AD7440 and the AD7450A use ad-
vanced design techniques to achieve very low power dissipation
at high throughput rates.
PRODUCT HIGHLIGHTS
1.
Operation with either 3 V or 5 V power supplies.
2.
High throughput with low power consumption.
With a 3 V supply, the AD7440/AD7450A offer 4 mW
max power consumption for 1 MSPS throughput.
3.
Fully differential analog input.
4.
Flexible power/serial clock speed management.
The conversion rate is determined by the serial clock,
allowing the power to be reduced as the conversion time
is reduced through the serial clock speed increase. These
parts also feature a shutdown mode to maximize power
efficiency at lower throughput rates.
5.
Variable voltage reference input.
6.
No pipeline delay.
Accurate control of the sampling instant via a CS input and
7.
once-off conversion control.
8.
ENOB > eight bits typically with 100 mV reference.
1
Protected by U.S. Patent Number 6,681,332.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
AD7440/AD7450A
FUNCTIONAL BLOCK DIAGRAM
V
DD
12-BIT
SUCCESSIVE
T/H
APPROXIMATION
ADC
SCLK
SDATA
CONTROL LOGIC
CS
Figure 1.
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.

AD7440 Summary of contents

  • Page 1

    ... PRODUCT HIGHLIGHTS 1. Operation with either power supplies. 2. High throughput with low power consumption. With supply, the AD7440/AD7450A offer 4 mW max power consumption for 1 MSPS throughput. 3. Fully differential analog input. 4. Flexible power/serial clock speed management. The conversion rate is determined by the serial clock, allowing the power to be reduced as the conversion time is reduced through the serial clock speed increase ...

  • Page 2

    ... Changes to Table 2 footnotes ............................................................. 5 Changes to Table 3 footnotes ............................................................. 7 Digital Inputs .............................................................................. 19 Reference ..................................................................................... 19 Single-Ended Operation............................................................ 20 Serial Interface ............................................................................ 21 Modes of Operation ....................................................................... 23 Normal Mode.............................................................................. 23 Power-Down Mode .................................................................... 23 Power-Up Time .......................................................................... 24 Power vs. Throughput Rate....................................................... 24 Microprocessor and DSP Interfacing ...................................... 25 Grounding and Layout Hints.................................................... 26 Evaluating the AD7440/AD7450A Performance................... 26 Outline Dimensions ....................................................................... 27 Ordering Guide............................................................................... 28 Rev Page ...

  • Page 3

    ... When in track-and-hold Typically 200 μA DD SOURCE 200 μA DD SOURCE I = 200 μA SINK Rev Page AD7440/AD7450A = 4. 5. MHz MSPS, SCLK S B Version 61 –74 –76 –83 – 2.5 10 ±0.5 ±0.5 ± ...

  • Page 4

    ... Because the input spans of V and V are both V IN+ IN– 5 The AD7440 is functional with a reference input from 100 mV and for V 6 The AD7440 is functional with a reference input from 100 mV and for V 7 Guaranteed by characterization. 8 Measured with a midscale dc input. 9 See the Power vs. Throughput section. Test Conditions/Comments ...

  • Page 5

    ... When in track-and-hold Typically 200 μA DD SOURCE 200 μA DD SOURCE I = 200 μA SINK Rev Page AD7440/AD7450A = 4. 5. MHz MSPS, SCLK S B Version 70 –76 –74 –76 –74 –89 – 2.5 12 ± ...

  • Page 6

    ... AD7440/AD7450A Parameter CONVERSION RATE Conversion Time 2 Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode Power Dissipation Normal Mode (Operational) Full Power-Down 1 Common-mode voltage. The input signal can be centered common-mode voltage in the range specified in Figure 28 and Figure 29. ...

  • Page 7

    ... DB9 DB8 Figure 3. AD7440 Serial Interface Timing Diagram Rev Page AD7440/AD7450A ) and timed from a voltage level 4. 5. MHz MSPS, SCLK 0 2.0 V for quoted in the Timing Specifications is the true bus relinquish ...

  • Page 8

    ... AD7440/AD7450A ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 4. Parameter V to GND GND IN GND IN– Digital Input Voltage to GND Digital Output Voltage to GND V to GND REF Input Current to Any Pin Except Supplies Operating Temperature Range Commercial (B Version) Storage Temperature Range Junction Temperature θ ...

  • Page 9

    ... The bits are clocked out on the falling edge of the SCLK input. The data stream of the AD7450A consists of four leading zeros followed by the 12 bits of conversion data, which are provided MSB first; the data stream of the AD7440 consists of four leading zeros, followed by the 10 bits of conversion data, followed by two trailing zeros. In both cases, the output coding is twos complement ...

  • Page 10

    ... The AD7440/AD7450A is tested using the CCIF standard of two input frequencies near the top end of the input bandwidth. In this case, the second-order terms are distanced in frequency from the original sine waves, while the third-order terms are at a frequency close to the input frequencies ...

  • Page 11

    ... ADC output at full-scale frequency the power of a 100 mV p-p sine wave applied to the ADC V frequency f . The frequency of this input varies from 1 kHz MHz. PSRR (dB) = 10log(Pf/ the power at frequency f in the ADC output; Pfs is the power at frequency f supply of DD Rev Page AD7440/AD7450A ) S in the ADC output. S ...

  • Page 12

    ... AD7440/AD7450A AD7440/AD7450A–TYPICAL PERFORMANCE CHARACTERISTICS T = 25° MSPS MHz, unless otherwise noted SCLK 100 FREQUENCY (kHz) Figure 7. AD7450A SINAD vs. Analog Input Frequency for Various Supply Voltages 0 –10 –20 –30 –40 –50 – –70 DD – ...

  • Page 13

    ... V Figure 17. Change in Zero-Code Error vs. Reference Voltage for DD 12.0 11 11.0 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 0 3.0 3 Figure 18. Change in ENOB vs. Reference Voltage for V DD Rev Page AD7440/AD7450A POSITIVE INL NEGATIVE INL 0.5 1.0 1.5 2.0 2.2 V (V) REF for the AD7450A for V REF 0.5 1.0 1.5 2.0 2.5 3.0 V (V) REF and 3 V for the AD7450A ...

  • Page 14

    ... SFDR = –83.1dB 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 400 500 = Rev Page 256 512 768 CODE Figure 21. Typical DNL for the AD7440 for 256 512 768 CODE Figure 22. Typical INL for the AD7440 for 1024 = 5 V 1024 ...

  • Page 15

    ... CAPACITIVE DAC C S SW1 CONTROL SW3 LOGIC SW2 C S REF COMPARATOR CAPACITIVE DAC Figure 24. ADC Conversion Phase /4096, and the LSB size of the AD7440 is REF × 1LSB = 2 V /4096 AD7450A REF × 1LSB = 2 V /1024 AD7440 REF 1 LSB 0 LSB +V – 1 LSB REF – ...

  • Page 16

    ... The conversion result is output in a 16-bit word with four leading zeros followed by the MSB of the 12-bit or 10-bit result. The 10-bit result of the AD7440 is followed by two trailing zeros. For more details on driving the differential inputs and setting up the common mode, refer to the Driving Differential Inputs section. μ ...

  • Page 17

    ... REF Analog Input Structure Figure 31 shows the equivalent circuit of the analog input structure of the AD7440/AD7450A. The four diodes provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV. This causes these diodes to become forward biased and start conducting into the substrate ...

  • Page 18

    ... Differential Amplifier An ideal method of applying differential drive to the AD7440/AD7450A is to use a differential amplifier such as the AD8138. This part can be used as a single-ended-to-differential amplifier differential-to-differential amplifier. In both cases, the analog input needs to be bipolar. It also provides common-mode level shifting and buffering of the bipolar input signal ...

  • Page 19

    ... Op Amp Pair An op amp pair can be used to directly couple a differential signal to the AD7440/AD7450A. The circuit configurations shown in Figure 35 and Figure 36 show how a dual op amp can be used to convert a single-ended signal into a differential signal for both a bipolar and unipolar input signal, respectively. The voltage applied to Point A sets up the common-mode voltage ...

  • Page 20

    ... REF Table 6. Examples of Suitable Voltage References Reference AD780 ADR421 ADR420 SINGLE-ENDED OPERATION When supplied with power supply, the AD7440/AD7450A can handle a single-ended input. The design of these devices is can range REF optimized for differential operation, so with a single-ended = 4. input, performance degrades. Linearity degrades by typically ...

  • Page 21

    ... AD7450A consists of four leading zeros followed by 12 bits of conversion data provided MSB first; the data stream of the AD7440 consists of four leading zeros, followed by the 10 bits of conversion data followed by two trailing zeros, which is also provided MSB first. In both cases, the output coding is twos complement ...

  • Page 22

    ... AD7440/AD7450A Timing Example 1 Having MHz and a throughput rate of 1 MSPS gives a SCLK cycle time of 1/Throughput = 1/1,000,000 = 1 μs A cycle consists 12.5(1 μs 2 SCLK ACQ Therefore 12.5(1/18 MHz μs ACQ t = 296 ns ACQ This 296 ns satisfies the requirement of 290 ns for t ...

  • Page 23

    ... ADC is then powered down for a relatively long duration between these bursts of conversions. When the AD7440/AD7450A are in the power-down mode, all analog circuitry is powered down. To enter power-down mode, the conversion process must be ...

  • Page 24

    ... the power-up time is one dummy cycle (1 μs), and the remaining conversion time is another cycle (1 μs), the AD7440/AD7450A can be said to dissipate 9.25 mW for 2 μs during each conversion cycle initiate the QUIET If the throughput rate = 100 kSPS, the cycle time = 10 μs and the average power dissipated during each cycle is (2/10) × ...

  • Page 25

    ... THROUGHPUT (kSPS) Figure 44. Power vs. Throughput Rate for Power-Down Mode MICROPROCESSOR AND DSP INTERFACING The serial interface on the AD7440/AD7450A allows the parts to be directly connected to many different microprocessors. This section explains how to interface the AD7440/AD7450A with some of the more common microcontroller and DSP serial interface protocols ...

  • Page 26

    ... GND pin on the AD7440/AD7450A as possible. Avoid running digital lines under the devices because this couples noise onto the die. The analog ground plane should be allowed to run under the AD7440/AD7450A to avoid noise coupling. The power supply lines to the AD7440/AD7450A should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line ...

  • Page 27

    ... Figure 48. 8-Lead Small Outline Transistor Package [SOT-23] (RT-8) Dimensions shown in millimeters 3.20 3.00 2.80 5. 3.20 4.90 3.00 4.65 1 2.80 4 PIN 1 0.65 BSC 0.95 0.85 1.10 MAX 0.75 0.15 0.38 0.23 0.00 0.22 0.08 COPLANARITY SEATING 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 49. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev Page AD7440/AD7450A 0.60 8° 0.45 4° 0.30 0° 0.80 8° 0.60 0° 0.40 ...

  • Page 28

    ... Evaluation board controller. This board is a complete unit allowing control and communicate with all Analog Devices’ evaluation boards ending in the CB designator. For a complete evaluation kit, order the ADC evaluation board (that is, the EVAL-AD7450ACB or EVAL-AD7440CB), the EVAL-CONTROL BRD2, and transformer. See the AD7440/AD7450A application note that accompanies the evaluation kit for more information. © ...