AD7453 Analog Devices, AD7453 Datasheet
AD7453
Specifications of AD7453
Related parts for AD7453
AD7453 Summary of contents
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... V to 5.25 V power supply and features throughput rates up to 555 kSPS. The part contains a low noise, wide bandwidth, differential track-and-hold amplifier (T/H) that can handle input frequen- cies up to 3.5 MHz. The reference voltage for the AD7453 is applied externally to the V pin and can range from 100 mV to REF ...
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... Changes to Reference Section................................................... 13 Changes to Timing Example 1.................................................. 14 8/03—Rev. 0: Initial Version Reference ..................................................................................... 13 Serial Interface ............................................................................ 13 Modes of Operation ....................................................................... 15 Normal Mode.............................................................................. 15 Power-Down Mode.................................................................... 15 Power-Up Time .......................................................................... 16 Power vs. Throughput Rate....................................................... 17 Microprocessor and DSP Interfacing ...................................... 17 Application Hints ....................................................................... 19 Evaluating the AD7453’s Performance .................................... 19 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 20 Rev Page ...
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... Straight (natural) binary AD7453 Unit dB min dB min dB min dB max dB max dB max dB max dB typ dB typ ns typ ps typ MHz typ MHz typ Bits LSB max LSB max LSB max LSB max µA max ...
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... Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave > 3.5 MHz) within the acquisition time may cause an incorrect result to be returned by the converter small dc input is applied provide a pseudo ground for V IN– 5 The AD7453 is functional with a reference input in the range 100 Guaranteed by characterization. 7 See Power vs. Throughput Rate section. ...
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... SCLK falling edge to SDATA three-state enabled Power-up time from full power-down t CONVERT DB11 DB10 Figure 2. AD7453 Serial Interface Timing Diagram Rev Page and timed from a voltage DD , unless otherwise noted. MAX QUIET DB2 DB1 ...
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... AD7453 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter V to GND GND IN GND IN– Digital Input Voltage to GND Digital Output Voltage to GND V to GND REF Input Current to Any Pin Except Supplies Operating Temperature Range Commercial (A, B Version) ...
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... Serial Data. Logic output. The conversion result from the AD7453 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream of the AD7453 consists of four leading zeros followed by the 12 bits of conversion data that are provided MSB first. The output coding is straight (natural) binary. ...
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... The AD7453 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves while the third-order terms are usually at a frequency close to the input frequencies ...
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... CODE Figure 8. Typical DNL for the AD7453 for V 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 1024 2048 CODE Figure 9. Typical INL for the AD7453 for V 9949 CODES 9000 8000 7000 6000 5000 4000 3000 2000 1000 27 CODES 24 CODES 0 2046 2047 2048 ...
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... AD7453 4.0 3.5 3.0 2.5 2.0 1.5 1.0 POSITIVE DNL 0.5 0 –0.5 NEGATIVE DNL –1 (V) REF Figure 11. Change in DNL vs. V REF POSITIVE INL 0 NEGATIVE INL –1 – (V) REF Figure 12. Change in INL vs. V REF 4 5 for for Rev ...
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... V IN+ V IN– ADC TRANSFER FUNCTION The output coding for the AD7453 is straight (natural) binary. The designed code transitions occur at successive LSB values (i.e., 1 LSB, 2 LSB, and so on). The LSB size is V ideal transfer characteristic of the AD7453 is shown in CAPACITIVE Figure 16. ...
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... Figure 18. Op Amp Configuration to Level Shift a Bipolar Input Signal Analog Input Structure Figure 19 shows the equivalent circuit of the analog input struc- +2.7V TO +5.25V ture of the AD7453. The four diodes provide ESD protection for SUPPLY 10µF the analog inputs. Care must be taken to ensure that the analog ...
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... INPUT FREQUENCY (kHz) Figure 21. THD vs. Analog Input Frequency for Various Supply Voltages DIGITAL INPUTS The digital inputs applied to the AD7453 are not limited by the maximum ratings that limit the analog inputs. Instead, the digital inputs applied, i.e., CS and SCLK, can and are not restricted by the ...
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... AD7453 Sixteen serial clock cycles are required to perform a conversion and to access data from the AD7453. CS going low provides the first leading zero to be read in by the microcontroller or DSP. The remaining data is then clocked out on the subsequent SCLK falling edges, beginning with the second leading zero. ...
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... This avoids accidental power-down due to glitches on the CS line. To exit this mode of operation and power up the AD7453 again, a dummy conversion is performed. On the falling edge the device begins to power up, and continues to power up as long held low until after the falling edge of the 10 SCLK. The device is fully powered up after 1 µ ...
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... CS . When running at the maximum throughput rate of 555 kSPS, the AD7453 powers up and acquires a signal within ±0.5 LSB in one dummy cycle. When powering up from power-down mode with a dummy cycle Figure 26, the track and-hold, which ...
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... For the same scenario the power dissipation during DD normal operation is 3.3 mW max. The AD7453 can now be said ∗ to dissipate 3.3 mW for 2.66 µs during each conversion cycle. The average power dissipated during each cycle with a throughput rate of 100 kSPS is therefore (2.66/10) × ...
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... PINS REMOVED FOR CLARITY Figure 29. Interfacing to the TMS320C5x/C54x AD7453 to DSP56xxx The connection diagram in Figure 30 shows how the AD7453 can be connected to the SSI (synchronous serial interface) of the DSP56xxx family of DSPs from Motorola. The SSI is operated in synchronous mode (SYN bit in CRB = 1) with internally generated 1-bit clock period frame sync for both Tx and Rx (Bit FSL1 = 1 and Bit FSL0 = 0 in CRB) ...
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... The analog ground plane should be allowed to run under the AD7453 to avoid noise coupling. The power supply lines to the AD7453 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. ...
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... The evaluation board controller is a complete unit allowing control and communicate with all Analog Devices evaluation boards ending in the CB designator. For a complete Evaluation Kit, you will need to order the ADC evaluation board, i.e., EVAL-AD7453CB, the EVAL-CONTROL BRD2, and transformer. See the AD7453 application note that accompanies the evaluation kit for more information. © ...