AD7674 Analog Devices, AD7674 Datasheet
AD7674
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AD7674 Summary of contents
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... Instrumentation Spectrum analysis Medical instruments GENERAL DESCRIPTION The AD7674 is an 18-bit, 800 kSPS, charge redistribution SAR, fully differential analog-to-digital converter that operates on a single 5 V power supply. The part contains a high speed 18-bit sampling ADC, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports ...
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... Initial Version Converter Operation .................................................................. 16 Typical Connection Diagram ................................................... 18 Power Dissipation versus Throughput .................................... 20 Conversion Control ................................................................... 20 Digital Interface .......................................................................... 20 Parallel Interface ......................................................................... 21 Serial Interface ............................................................................ 21 Master Serial Interface ............................................................... 21 Slave Serial Interface .................................................................. 22 Microprocessor Interfacing ....................................................... 24 Application Hints ........................................................................... 25 Layout .......................................................................................... 25 Evaluating the AD7674’s Performance .................................... 25 Outline Dimensions ....................................................................... 26 Ordering Guide .......................................................................... 26 Rev Page ...
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... 100 kHz kHz kHz 100 kHz kHz 4.096 V IN REF kHz, –60 dB input IN Full-scale step Rev Page AD7674 Typ Max Unit Bits +V V REF AVDD 100 μA 1.25 μs 800 kSPS 1 ms 1.5 μs 666 kSPS 1 ...
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... AD7674 Parameter REFERENCE External Reference Voltage Range REF Voltage with Reference Buffer Reference Buffer Input Voltage Range REFBUFIN Input Current REF Current Drain DIGITAL INPUTS Logic Levels DIGITAL OUTPUTS 5 Data Format 6 Pipeline Delay POWER SUPPLIES ...
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... Rev Page Min Typ 10 1.25/1.5/1. 250 25/275/525 Table 4 1/1.25/1 pF; otherwise, the load maximum. L AD7674 Max Unit ns μ 1/1.25/1.5 μ 1/1.25/1.5 μ 1/1.25/1.5 μ ...
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... AD7674 Table 4. Serial Clock Timings in Master Read after Convert DIVSCLK[1] DIVSCLK[0] SYNC to SCLK First Edge Delay Minimum Internal SCLK Period Minimum Internal SCLK Period Maximum Internal SCLK HIGH Minimum Internal SCLK LOW Minimum SDOUT Valid Setup Time Minimum SDOUT Valid Hold Time Minimum ...
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... ABSOLUTE MAXIMUM RATINGS Table 5. AD7674 Absolute Maximum Ratings Parameter Analog Inputs 2 2 IN+ , IN– , REF, REFBUFIN, REFGND to AGND Ground Voltage Differences AGND, DGND, OGND Supply Voltages AVDD, DVDD, OVDD AVDD to DVDD, AVDD to OVDD DVDD to OVDD Digital Inputs 3 Internal Power Dissipation 4 Internal Power Dissipation ...
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... When MODE = 0 (18-bit interface mode), this pin is Bit 1 of the parallel port data output bus. In all other modes, this input pin controls the form in which data is output, as shown in Table 7. AGND 1 PIN 1 AVDD 2 INDICATOR MODE0 3 MODE1 4 D0/OB/2C 5 AD7674 WARP 6 TOP VIEW IMPULSE 7 (Not to Scale) D1/A0 8 D2/ Figure 4 ...
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... When MODE = 3 (serial mode), this output, part of the serial port, is used as a serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7674 provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C ...
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... Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled also used to gate the external clock. 33 RESET DI Reset Input. When set to a logic HIGH, reset the AD7674. Current conversion, if any, is aborted. If not used, this pin could be tied to DGND Power-Down Input ...
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... Aperture delay is a measure of the acquisition performance and is measured from the falling edge of the CNVST input to when the input signal is held for a conversion. Transient Response Transient response is the time required for the AD7674 to achieve its rated accuracy after a full-scale step function is applied to its input. Rev Page ...
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... AD7674 TYPICAL PERFORMANCE CHARACTERISTICS 2.5 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 0 65536 131072 CODE Figure 5. Integral Nonlinearity vs. Code 70000 59121 58556 60000 50000 40000 30000 20000 10000 5073 2004C 2004D 2004E 2004F 20050 20051 20052 20053 CODE IN HEX Figure 6. Histogram of 131,072 Conversions Input at the Code Transition ...
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... Rev Page –1.5 –1.0 –0.5 NEGATIVE DNL (LSB) SNR S/(N+D) ENOB 10 100 FREQUENCY (kHz) 03083-0-015 Figure 15. SNR, S/(N+D), and ENOB vs. Frequency SFDR THIRD HARMONIC THD SECOND HARMONIC 10 100 FREQUENCY (kHz) 03083-0-016 AD7674 0 03083-0-014 16.5 16.0 15.5 15.0 14.5 14.0 13.5 1000 140 120 100 1000 ...
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... AD7674 105 104 103 102 101 100 –60 –50 –40 –30 INPUT LEVEL (dB) Figure 17. SNR and S/(N+D) vs. Input Level 100 SNR 99 S/(N+ –55 –35 – TEMPERATURE (°C) Figure 18. SNR, S/(N+D), and ENOB vs. Temperature –100 –110 THD –120 SECOND HARMONIC – ...
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... AVDD (V) Figure 23. Zero Error, Positive and Negative Full Scale vs. Supply 5.25 5.50 0 03083-0-023 Rev Page OVDD = 2.7V @ 85°C OVDD = 2.7V @ 25°C OVDD = 5V @ 85°C OVDD = 5V @ 25°C 50 100 150 C (pF) L Figure 24. Typical Delay vs. Load Capacitance C AD7674 200 03083-0-024 L ...
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... ADC that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. The AD7674 can be operated from a single 5 V supply and can be interfaced to either digital logic housed in a 48-lead LQFP tiny 48-lead LFCSP package that offers space savings and allows for flexible configurations as either a serial or parallel interface ...
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... Transfer Functions Except in 18-bit interface mode, the AD7674 offers straight binary and twos complement output coding when using OB See Figure 26 and Table 8 for the ideal transfer characteristic. 111...111 111...110 111...101 000...010 000...001 000...000 –FS – ...
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... MHz typ reduces any undesirable aliasing effect and limits the noise coming from the inputs. Because the input impedance of the AD7674 is very high, the part can be driven directly by a low impedance source without gain error. This allows the user to put an external 1-pole RC ...
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... LSB/°C. Power Supply The AD7674 uses three sets of power supply pins: an analog 5 V supply (AVDD), a digital 5 V core supply (DVDD), and a digital output interface supply (OVDD). The OVDD supply defines the output logic level and allows direct interface with any logic working between 2 ...
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... CNVST generation clock it with a high frequency low jitter clock, as shown in Figure 27. In Impulse mode, conversions can be initiated automatically. If CNVST is held low when BUSY goes low, the AD7674 controls the acquisition phase and automatically initiates a new conversion. By keeping CNVST low, the AD7674 keeps the conversion process running by itself ...
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... The AD7674 is configured to generate and provide the serial data clock SCLK when the EXT/ INT pin is held low. The AD7674 also generates a SYNC signal to indicate to the host when the serial data is valid. The serial clock SCLK and the SYNC signal can be inverted if desired. Depending on the RDC/SDIN input, the data can be read after each conversion or during the following conversion ...
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... A discontinuous clock can be either normally high or normally low when inactive. Figure 42 and Figure 43 show the detailed timing diagrams of these methods. While the AD7674 is performing a bit decision important that voltage transients not occur on digital input/output pins or Rev Page INVSCLK = INVSYNC = 0 ...
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... Also, data can be read at speeds MHz, accommodating both slow digital host interface and the fastest serial reading. Finally, in this mode only, the AD7674 provides a daisy-chain feature using the RDC/SDIN input pin to cascade multiple converters together. This feature is useful for reducing component count and wiring connections when desired (for instance, in isolated multiconverter applications) ...
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... Figure 45 shows an interface diagram between the AD7674 and SCLK the SPI equipped ADSP-219x. To accommodate the slower speed of the DSP, the AD7674 acts as a slave device, and data must be read after conversion. This mode also allows the daisy- 03083-0-044 chain feature. The convert command could be initiated in response to an internal timer interrupt ...
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... This will reduce the effect of feedthrough through the board. The power supply lines to the AD7674 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is also important to lower the supply’ ...
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... SEATING PLANE ORDERING GUIDE Model Temperature Range 1 AD7674ASTZ −40°C to +85°C AD7674ASTZL −40°C to +85°C AD7674ACPZ −40°C to +85°C AD7674ACPZRL −40°C to +85°C 2 EVAL-AD7674CBZ EVAL-CED1Z 3 3 EVAL-CONTROL BRD2Z EVAL-CONTROL BRD3Z RoHS Compliant Part. 2 This board can be used as a standalone evaluation board or in conjunction with a capture board for evaluation/demonstration purposes. ...
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... NOTES Rev Page AD7674 ...
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... AD7674 NOTES ©2003–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03083-0-6/09(A) Rev Page ...