AD9864 Analog Devices, AD9864 Datasheet - Page 25

• Manufacturer Part Number: AD9864
• Description: IF Digitizing Subsystem
• Manufacturer: Analog Devices

Specifications of AD9864

• Resolution (bits): 24bit
• # Chan: 1
• Sample Rate: 18MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Uni
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

The 14-bit reference counter and 13-bit N-divider counter can be
programmed via registers CKR and CKN. The clock frequency,
f
The charge pump current is programmable via the CKI register
from 0.625 mA to 5.0 mA using the equation
The fast acquire subcircuit of the charge pump is controlled by
the CKFA register in the same manner the LO synthesizer is
controlled by the LOFA register. An on-chip lock detect func-
tion (enabled by the CKF bit) automatically increases the out-
put current for faster settling during channel changes. The syn-
thesizer may also be disabled using the CK standby bit located
in the STBY register.
V
f
The AD9864 clock synthesizer circuitry includes a negative
resistance core so that only an external LC tank circuit with a
varactor is needed to realize a voltage controlled clock oscillator
(VCO). Figure 40 shows the external components required to
complete the clock synthesizer along with the equivalent input
circuitry of the CLK input. The resonant frequency of the VCO
is approximately determined by L
capacitance of C
should be selected to provide a sufficient tuning range to ensure
proper locking of the clock synthesizer.
The bias, I
grammable settings. Lower equivalent Q of the LC tank circuit
may require a higher bias setting of the negative-resistance core
to ensure proper oscillation. R
common-mode voltage at CLKP and CLKN is approximately
1.6 V. The synthesizer may be disabled via the CK standby bit
to allow the user to employ an external synthesizer and/or VCO
in place of those resident on the IC. Note that if an external
CLK
OSC
CM
, is related to the reference frequency by the equation
= VDDC – R
> 1/{2π × (L
I
f
CLK
PUMP
IOUTC
15
Are Required to Realize a Complete Clock Synthesizer
Figure 40. External Loop Filter, Varactor, and LC Tank
BIAS
=
BIAS
OSC
=
R
(
CKN
F
, of the negative-resistance core has four pro-
FILTER
(
LOOP
CKI
× (C
× I
C
C
OSC
Z
BIAS
P
VARACTOR
AD9864
/
+
CKR
and C
> 1.6V
1 ×
CLK OSC. BIAS
)
R
D
×
. 0
||C
625
VAR
f
OSC
REF
C
C
. As a result, L
OSC
))
VAR
mA
1/2
BIAS
)
}
19
OSC
should be selected so the
2
CLKP
L
and the series equivalent
OSC
20
OSC
I
0.40mA, OR 0.65mA
BIAS
VDDC = 3.0V
R
0.1µF
CLKN
BIAS
, C
= 0.15mA, 0.25mA,
OSC
, and C
VAR
Rev. 0 | Page 25 of 44
(5)
(6)
CLK source or VCO is used, the clock oscillator must be
disabled via the CKO standby bit.
The phase noise performance of the clock synthesizer is
dependent on several factors, including the CLK oscillator I
setting, charge pump setting, loop filter component values, and
internal f
measured phase noise attributed to the clock synthesizer varies
(relative to an external f
charge pump setting for a –31 dBm IFIN signal at 73.35 MHz
with an external LO signal at 71.1 MHz. Figure 41 shows that
the optimum phase noise is achieved with the highest I
(CKO) setting, while Figure 42 shows that the higher charge
pump values provide the optimum performance for the given
loop filter configuration. The AD9864 clock synthesizer and
oscillator were set up to provide an f
external f
values were selected for the synthesizer: R
C
= Toshiba 1SV228 Varactor.
Z
IF = 71.1 MHz, IFIN = –31 dBm, f
= 0.68 µF, C
(CLK SYN Settings: CKI = 7, CLR = 56, and CLN = 60 with f
Settings: CKO Bias = 3, CKR = 56, and CKN = 60 with f
–100
–110
–120
–130
–140
–100
–110
–120
–130
–140
Figure 41. CLK Phase Noise vs. I
Figure 42. CLK Phase Noise vs. I
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
IF = 71.1 MHz, IFIN = –31 dBm, f
0
0
–25
–25
REF
REF
setting. Figure 41 and Figure 42 show how the
of 16.8 MHz. The following external component
–20
–20
P
CKO = 1
= 0.1 µF, C
–15
–15
CK0 = 0
CP = 2
–10
–10
CP = 0
FREQUENCY OFFSET (kHz)
FREQUENCY OFFSET (kHz)
CLK
) as a function of the I
–5
OSC
5
CLK
= 91 pF, L
BIAS
BIAS
= 18 MHz, f
0
0
CLK
Setting (CKO) (IF = 73.35 MHz,
Setting (CKO) (IF = 73.35 MHz,
= 18 MHz, f
CLK
5
5
CP = 4
of 18 MHz from an
REF
OSC
CP = 6
EXT CLK
F
CKO = 3
10
10
CKO = 2
= 390 Ω, R
= 16.8 MHz) (CLK SYN
EXT CLK
= 1.2 µH, and C
REF
15
15
= 16.8 MHz)
BIAS
REF
REF
= 300 kHz
20
20
= 300 kHz)
setting and
AD9864
D
BIAS
= 2 kΩ,
25
25
BIAS
VAR