AD7908 Analog Devices, AD7908 Datasheet - Page 21

• Manufacturer Part Number: AD7908
• Description: 8-Channel, 1 MSPS, 8-Bit ADC with Sequencer in 20-Lead TSSOP
• Manufacturer: Analog Devices

Specifications of AD7908

• Resolution (bits): 8bit
• # Chan: 8
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref),Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: SOP

inputs. Instead, the digital inputs applied can go to 7 V and are
not restricted by the AV
Another advantage of SCLK, DIN, and CS not being restricted
by the AV
sequencing issues are avoided. If CS , DIN, or SCLK are applied
before AV
the analog inputs if a signal greater than 0.3 V was applied prior
to AV
V
The AD7908/AD7918/AD7928 also have the V
V
V
processors. For example, if the AD7908/AD7918/AD7928 were
operated with an AV
from a 3 V supply. The AD7908/AD7918/AD7928 have better
dynamic performance with an AV
to interface to 3 V processors. Care should be taken to ensure
V
Absolute Maximum Ratings section.
Reference
An external reference source should be used to supply the 2.5 V
reference to the AD7908/AD7918/AD7928. Errors in the
reference source results in gain errors in the AD7908/
AD7918/AD7928 transfer function and adds to the specified
full-scale errors of the part. A capacitor of at least 0.1 μF should
be placed on the REF
AD7908/AD7918/AD7928 include the AD780, REF192,
AD1582, ADR03, ADR381, ADR391, and ADR421.
If 2.5 V is applied to the REF
either be 0 V to 2.5 V or 0 V to 5 V, depending on the setting of
the RANGE bit in the control register.
MODES OF OPERATION
The AD7908/AD7918/AD7928 have a number of different
modes of operation. These modes are designed to provide
flexible power management options. These options can be
chosen to optimize the power dissipation/throughput rate ratio
for differing application requirements. The mode of operation
of the AD7908/AD7918/AD7928 is controlled by the power
management bits, PM1 and PM0, in the control register, as
detailed in Table 9. When power supplies are first applied to the
AD7908/AD7918/AD7928, care should be taken to ensure that
the part is placed in the required mode of operation (see
Powering Up the AD7908/AD7918/AD7928 section).
Normal Mode (PM1 = PM0 = 1)
This mode is intended for the fastest throughput rate
performance, as the user does not have to worry about any
power-up times with the AD7908/AD7918/AD7928 remaining
fully powered at all times. Figure 21 shows the general diagram
of the operation of the AD7908/AD7918/AD7928 in this mode.
DRIVE
DRIVE
DRIVE
DRIVE
DD
controls the voltage at which the serial interface operates.
allows the ADC to easily interface to both 3 V and 5 V
does not exceed AV
.
DD
DD
, there is no risk of latch-up as there would be on
+ 0.3 V limit is the fact that power supply
DD
IN
of 5 V, the V
pin. Suitable reference sources for the
DD
DD
+ 0.3 V limit as on the analog inputs.
IN
by more than 0.3 V. See the
pin, the analog input range can
DD
DRIVE
of 5 V while still being able
pin could be powered
DRIVE
feature.
Rev. D | Page 21 of 32
The conversion is initiated on the falling edge of CS and the
track-and-hold enters hold mode as described in the
Interface
AD7928 on the DIN line during the first 12 clock cycles of the
data transfer are loaded into the control register (provided
WRITE bit is set to 1). If data is to be written to the SHADOW
register (SEQ = 0, SHADOW = 1 on previous write), data
presented on the DIN line during the first 16 SCLK cycles is
loaded into the SHADOW register. The part remains fully
powered up in normal mode at the end of the conversion as
long as PM1 and PM0 are both loaded with 1 on every data
transfer.
Sixteen serial clock cycles are required to complete the
conversion and access the conversion result. The track-and-
hold goes back into track on the 14th SCLK falling edge. CS can
then idle high until the next conversion or can idle low until
sometime prior to the next conversion, effectively idling CS low.
Once a data transfer is complete (DOUT has returned to three-
state), another conversion can be initiated after the quiet time,
t
Full Shutdown Mode (PM1 = 1, PM0 = 0)
In this mode, all internal circuitry on the AD7908/AD7918/
AD7928 is powered down. The part retains information in the
control register during full shutdown. The AD7908/AD7918/
AD7928 remains in full shutdown until the power management
bits in the control register, PM1 and PM0, are changed.
If a write to the control register occurs while the part is in full
shutdown, with the power management bits changed to PM0 =
PM1 = 1, normal mode, the part begins to power up on the CS
rising edge. The track-and-hold that was in hold while the part was
in full shutdown returns to track on the 14th SCLK falling edge.
To ensure that the part is fully powered up, t
have elapsed before the next CS falling edge.
the general diagram for this sequence.
Auto Shutdown Mode (PM1 = 0, PM0 = 1)
In this mode, the AD7908/AD7918/AD7928 automatically
enters shutdown at the end of each conversion when the control
register is updated. When the part is in shutdown, the track and
hold is in hold mode. Figure 23 shows the general diagram of
QUIET
DOUT
NOTES
1. CONTROL REGISTER DATA IS LOADED ON FIRST 12 SCLK CYCLES.
2. SHADOW REGISTER DATA IS LOADED ON FIRST 16 SCLK CYCLES.
SCLK
, has elapsed by bringing CS low again.
DIN
CS
section. The data presented to the AD7908/AD7918/
DATA IN TO CONTROL/SHADOW REGISTER
IDENTIFIER BITS + CONVERSION RESULT
1
Figure 21. Normal Mode Operation
1 LEADING ZERO + 3 CHANNEL
AD7908/AD7918/AD7928
12
POWER UP
Figure 22
16
, should
Serial
shows