AD7654 Analog Devices, AD7654 Datasheet
AD7654
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AD7654 Summary of contents
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... Superior INL and No Missing Codes. The AD7654 has a maximum integral nonlinearity of 3.5 LSB with no missing 16-bit codes. 4. Single-Supply Operation. The AD7654 operates from a single 5 V supply. In impulse mode, its power dissipation decreases with throughput. 5. Serial or Parallel Interface. Versatile parallel or 2-wire serial interface arrangement is compatible with both 3 V and 5 V logic ...
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... Serial Interface ............................................................................ 20 Master Serial Interface............................................................... 20 Slave Serial Interface .................................................................. 22 Microprocessor Interfacing....................................................... 24 SPI Interface (ADSP-219x) ....................................................... 24 Application Hints ........................................................................... 25 Layout .......................................................................................... 25 Evaluating the AD7654 Performance ...................................... 25 Outline Dimensions ....................................................................... 26 Ordering Guide .......................................................................... 27 11/04—Rev Rev. A Changes to Figure 7........................................................................ 12 Changes to Figure 18...................................................................... 15 Changes to Figure 19...................................................................... 16 Changes to Voltage Reference Input Section .............................. 17 Changes to Conversion Control Section ...
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... kHz 87 100 kHz 100 kHz, −60 dB Input 100 kHz IN Full-scale step 2.3 500 kSPS throughput −0.3 +2.0 −1 −1 Rev Page AD7654 Typ Max Unit Bits REF +0 μA 2 μs 500 kSPS 2.25 μs 444 kSPS 3 +3 ...
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... AD7654 Parameter DIGITAL OUTPUTS 6 Data Format 7 Pipeline Delay POWER SUPPLIES Specified Performance AVDD DVDD OVDD 9 Operating Current AVDD DVDD OVDD Power Dissipation 11 TEMPERATURE RANGE Specified Performance 1 See the Analog Inputs section. 2 Linearity is tested using endpoints, not best fit. 3 LSB means least significant bit. Within the input range, one LSB is 76.294 μV. ...
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... Rev Page AD7654 Min Typ Max Unit 5 ns 2/2.25 μ 1.75/2 μ 1.75/2 μs 250 1/1.25 μ 0.75 μs 250 1.75/2 μs ...
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... AD7654 Parameter SLAVE SERIAL INTERFACE MODES (see Figure 32 and Figure 33) External SCLK Setup Time External SCLK Active Edge to SDOUT Delay SDIN Setup Time SDIN Hold Time External SCLK Period External SCLK High External SCLK Low 1 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load serial master read during convert mode ...
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... Rev Page 1.6mA OL TO OUTPUT 1.4V PIN C L 60pF* I 500µ 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. L Figure 2. Load Circuit for Digital Interface Timing (SDOUT, SYNC, SCLK Outputs pF DELAY 2V 2V 0.8V 0.8V Figure 3. Voltage Reference Levels for Timing AD7654 ...
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... When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC signal in Master modes. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW AGND 1 PIN 1 AVDD BYTESWAP 4 A/B 5 AD7654 DGND 6 TOP VIEW (Not to Scale) IMPULSE 7 SER/PAR D2/DIVSCLK[0] ...
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... Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled also used to gate the external serial clock. 33 RESET DI Reset Input. When set to a logic HIGH, reset the AD7654. Current conversion if any is aborted. If not used, this pin could be tied to DGND Power-Down Input ...
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... AD7654 1 Pin No. Mnemonic Type Description 35 CNVST DI Start Conversion. A falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. In impulse mode (IMPULSE = HIGH), if CNVST is held LOW when the acquisition phase (t immediately started. 37 REF AI This input pin is used to provide a reference to the converter. ...
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... Aperture delay is a measure of acquisition performance and is measured from the falling edge of the CNVST input to when the input signals are held for a conversion. Transient Response The time required for the AD7654 to achieve its rated accuracy after a full-scale step function is applied to its input. Rev Page AD7654 ...
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... AD7654 TYPICAL PERFORMANCE CHARACTERISTICS –1 –2 –3 –4 –5 0 16384 32768 CODE Figure 5. Integral Nonlinearity vs. Code 8000 7288 7220 7000 6000 5000 4000 3000 2000 953 903 1000 7FBF 7FC0 7FC1 7FC2 7FC3 7FC4 7FC5 CODE IN HEX Figure 6 ...
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... NORMAL AVDD NORMAL DVDD IMPULSE AVDD IMPULSE DVDD OVDD 2.7V 10 100 SAMPLING RATE (kSPS) Figure 15. Operating Currents vs. Sample Rate OVDD = 2.7V @ 85°C OVDD = 2.7V @ 25°C OVDD = 5V @ 85°C OVDD = 5V @ 25°C 50 100 150 C (pF) L Figure 16. Typical Delay vs. Load Capacitance C AD7654 105 125 1000 200 L ...
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... The AD7654 can also be used as a 4-channel ADC with two pairs simultaneously sampled. The AD7654 can be operated from a single 5 V supply and be interfaced to either digital logic housed in a 48-lead LQFP or tiny 48-lead LFCSP that combines space savings and allows flexible configurations as either a serial or parallel interface ...
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... DVDD OVDD REF REF A NOTE 1 REF B REFGND INA1 AD7654 INA2 INAN INB1 INB2 INBN IS 47µF. SEE VOLTAGE REFERENCE INPUT SECTION. REF Rev Page AD7654 DIGITAL SUPPLY (3.3V OR 5V) + 100nF 10µF OGND SERIAL PORT SCLK SDOUT BUSY µC/µP/ 50Ω DSP CNVST D ...
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... This one-pole filter with a typical −3 dB cutoff frequency of 10 MHz reduces undesirable aliasing effects and limits the noise coming from the inputs. Because the input impedance of the AD7654 is very high, the AD7654 can be driven directly by a low impedance source without gain error. To further improve the noise filtering of the ...
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... Figure 21. This feature makes the AD7654 ideal for very low power battery applications. Note that the digital interface remains active even during the acquisition phase ...
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... Figure 18. In impulse mode, conversions can be automatically initiated. If CNVST is held low when BUSY is low, the AD7654 controls the acquisition phase and automatically initiates a new conversion. By keeping CNVST low, the AD7654 keeps the conversion process running by itself ...
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... Channel A data is updated only after Channel B is converted. DATA BUS Rev Page HI-Z HIGH BYTE LOW BYTE HI-Z LOW BYTE HIGH BYTE Figure 27. 8-Bit Parallel Interface CS RD A/B HI-Z CHANNEL A CHANNEL Figure 28 Channel Reading AD7654 HI HI-Z HI-Z ...
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... AD7654 SERIAL INTERFACE The AD7654 is configured to use the serial interface when the SER/ PAR is held high. The AD7654 outputs 32 bits of data, MSB first, on the SDOUT pin. The order of the channels being output is also controlled When high, Channel A is output first; when low, Channel B is output first. This data is synchronized with the 32 clock pulses provided on the SCLK pin ...
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... D15 D14 D0 D15 RDC/SDIN = 1 INVSCLK = INVSYNC = D15 D14 Rev Page AD7654 A A ...
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... Figure 32 and Figure 33 show the detailed timing diagrams of these methods. While the AD7654 is performing a bit decision important that voltage transients not occur on digital input/output pins or degradation of the conversion result could occur. This is ...
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... Figure 33. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert) INVSCLK = D13 D13 INVSCLK = D13 Rev Page AD7654 A D15 D14 D15 D14 A ...
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... Figure 34 shows an interface diagram between the AD7654 and the SPI equipped ADSP-219x. To accommodate the slower speed of the DSP, the AD7654 acts as a slave device and data must be read after conversion. This mode also allows the daisy- chain feature. The convert command can be initiated in response to an internal timer interrupt ...
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... Additionally, low ESR 10 μF capacitors should be located near the ADC to further reduce low frequency ripple. The DVDD supply of the AD7654 can be a separate supply or can come from the analog supply AVDD or the digital interface supply OVDD. When the system digital supply is noisy or when ...
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... AD7654 OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW 7.00 BSC SQ PIN 1 INDICATOR TOP VIEW 1.00 12° MAX 0.85 0.80 SEATING PLANE 0.75 1.60 0.60 MAX 0.45 0.20 0.09 7° 3.5° 0° 0.08 MAX VIEW A COPLANARITY LEAD PITCH COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 35. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters ...
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... AD7654ACPZ –40°C to +85°C 1 AD7654ACPZRL –40°C to +85°C AD7654AST –40°C to +85°C AD7654ASTRL –40°C to +85°C 1 AD7654ASTZ –40°C to +85°C AD7654ASTZRL 1 –40°C to +85°C 2 EVAL-AD7654CB 3 EVAL-CONTROL BRD2 3 EVAL-CONTROL BRD3 free part. ...
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... AD7654 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03057–0–11/05(B) Rev Page ...