AD7663 Analog Devices, AD7663 Datasheet
AD7663
Specifications of AD7663
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AD7663 Summary of contents
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... The AD7663 is a 250 kSPS charge redistribution, 16-bit SAR ADC with various bipolar and unipolar input ranges. 2. Single-Supply Operation The AD7663 operates from a single 5 V supply and dissipates only 35 mW typical. Its power dissipation decreases with the throughput to, for instance, only 15 µ 100 SPS throughput. It consumes 7 µ ...
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... AD7663–SPECIFICATIONS Parameter RESOLUTION ANALOG INPUT Voltage Range Common-Mode Input Voltage Analog Input CMRR Input Impedance THROUGHPUT SPEED Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error No Missing Codes Transition Noise 2 Bipolar Zero Error , MIN MAX 2 Bipolar Full-Scale Error , MIN ...
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... INA(R) REF REF REF INGND INGND V IN Min Typ Max 1. 1.25 2. 9.5 4 AD7663 Unit °C Input 1 Impedance 5.85 kW 3.41 kW 2.56 kW 3.41 kW 2.56 kW Note 3 Unit ns µs ns µ µs µs ns µ µ ...
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... AD7663 TIMING SPECIFICATIONS (continued) Parameter Refer to Figures 17 and 18 (Master Serial Interface Modes) CS HIGH to SYNC HI-Z CS HIGH to Internal SCLK HI-Z CS HIGH to SDOUT HI-Z BUSY HIGH in Master Serial Read after Convert CNVST LOW to SYNC Asserted Delay (Master Serial Read after Convert) SYNC Deasserted to BUSY LOW Delay ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7663 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... AD7663 Pin No. Mnemonic Type Description 1 AGND P Analog Power Ground Pin. 2 AVDD P Input Analog Power Pin. Nominally Connect. 44–48 4 BYTESWAP DI Parallel Mode Selection (8/16 Bit). When LOW, the LSB is output on D[7:0] and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0]. ...
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... DI enabled also used to gate the external clock. 33 RESET DI Reset Input. When set to a logic HIGH, reset the AD7663. Current conversion, if any, is aborted. If not used, this pin could be tied to DGND Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are inhibited after the current one is completed ...
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... Aperture Delay A measure of the acquisition performance measured from the falling edge of the CNVST input to when the input signal is held for a conversion. Transient Response The time required for the AD7663 to achieve its rated accuracy after a full-scale step function is applied to its input. –8– ...
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... TPC 5. Histogram of 16,384 Conversions Input at the Code Center –100 –120 –140 –160 –180 –0.9 –0.6 –0.3 –9– AD7663 6802 6745 1800 1000 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8004 8005 CODE IN HEXA 8032 3944 3902 ...
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... AD7663 100 95 SNR 90 SINAD FREQUENCY – kHz TPC 7. SNR, S/(N+D), and ENOB vs. Frequency –80 –70 –60 –50 –40 –30 INPUT LEVEL – dB TPC 8. SNR vs. Input Level 96 THD 93 90 SNR 87 84 –55 –35 – TEMPERATURE – C TPC 9. SNR and THD vs. Temperature 16.0 – ...
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... The AD7663 can be operated from a single 5 V supply and can be interfaced to either digital logic housed in a 48-lead LQFP package or a 48-lead LFCSP package that combines space savings and flexible configurations as either serial or parallel inter- face ...
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... Transfer Functions Using the OB/2C digital input, the AD7663 offers two output codings: straight binary and twos complement. The ideal transfer characteristic for the AD7663 is shown in Figure 4 and Table III. TYPICAL CONNECTION DIAGRAM Figure 5 shows a typical connection diagram for the AD7663. Different circuitry shown on this diagram is optional and is discussed in the figure’ ...
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... THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 6. WITH 0V TO 2.5V RANGE ONLY. SEE ANALOG INPUTS SECTION. 7. OPTION. SEE POWER SUPPLY SECTION. 8. OPTIONAL LOW JITTER CNVST. SEE CONVERSION CONTROL SECTION. Figure 5. Typical Connection Diagram (±10 V Range Shown) Figure 6 shows a simplified analog input section of the AD7663. AVDD 4R IND 4R ...
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... Except when using the 2.5 V analog input voltage range, the AD7663 has to be driven by a very low impedance source to avoid gain errors. That can be done by using a driver amplifier whose choice is eased by the primarily resistive analog input circuitry of the AD7663 ...
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... AD7663. REV. B Power Supply The AD7663 uses three sets of power supply pins: an analog 5 V supply AVDD, a digital 5 V core supply DVDD, and a digital input/output interface supply OVDD. The OVDD supply allows direct interface with any logic working between 2.7 V and DVDD + 0 ...
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... CNVST generation least to clock it with a high frequency, low jitter clock as shown in Figure 5. For other applications, conversions can be automatically initiated. If CNVST is held low when BUSY is low, the AD7663 controls the acquisition phase and then automatically initiates a new conversion. By keeping CNVST low, the AD7663 keeps the conversion process running by itself ...
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... MASTER SERIAL INTERFACE Internal Clock The AD7663 is configured to generate and provide the serial data clock SCLK when the EXT/INT pin is held LOW. It also generates a SYNC signal to indicate to the host when the serial data is valid. ...
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... AD7663 CS CNVST BUSY t 29 SYNC t 14 SCLK t 15 SDOUT t 16 Figure 17. Master Serial Data Timing for Reading (Read after Convert) CS, RD CNVST BUSY t 17 SYNC SCLK t 18 SDOUT Figure 18. Master Serial Data Timing for Reading (Read Previous Conversion during Convert) ...
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... A discontinuous clock can be either normally high or normally low when inactive. Figures 19 and 21 show the detailed timing diagrams of these methods. While the AD7663 is performing a bit decision important that voltage transients not occur on digital input/output pins or degradation of the conversion result could occur. This is par- ...
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... INVSCLK Figure 22. Interfacing the AD7663 to SPI Interface ADSP-21065L in Master Serial Interface As shown in Figure 23, the AD7663 can be interfaced to the ADSP-21065L using the serial interface in Master Mode without any glue logic required. This mode combines the advantages of reducing the wire connections and being able to read the data during or after conversion at maximum speed transfer (DIVSCLK[0:1] both low ...
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... This will reduce the effect of feedthrough through the board. The power supply lines to the AD7663 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is also impor- tant to lower the supplies’ ...
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... AD7663 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE ROTATED 90 CCW 7.00 BSC SQ PIN 1 INDICATOR TOP VIEW 1.00 12 MAX 0.90 0.80 0.20 REF SEATING PLANE OUTLINE DIMENSIONS 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 0.75 1.60 0.60 MAX 0.45 1 SEATING PLANE 10 6 0.20 2 0.09 VIEW 0.10 MAX 0.50 COPLANARITY BSC VIEW A COMPLIANT TO JEDEC STANDARDS MS-026BBC ...
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... Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Edits to PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Addition of TPC Edits to CIRCUIT INFORMATION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Edits to Table III . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Edits to Voltage Reference Input and Power Supply sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Edits to ADSP-21065L in Master Serial Interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 New Package Outline Added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 REV. B –23– AD7663 Page ...
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