AD6644

Manufacturer Part NumberAD6644
Description14-Bit, 40 MSPS/65 MSPS Analog-to-Digital Converter
ManufacturerAnalog Devices
AD6644 datasheet
 


Specifications of AD6644

Resolution (bits)14bit# Chan1
Sample Rate65MSPSInterfacePar
Analog Input TypeDiff-UniAin Range2.2 V p-p
Adc ArchitecturePipelinedPkg TypeQFP
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FEATURES
65 MSPS guaranteed sample rate
40 MSPS version available
Sampling jitter < 300 fs
100 dB multitone SFDR
1.3 W power dissipation
Differential analog inputs
Pin compatible to AD6645
Twos complement digital output format
3.3 V CMOS compatible
Data-ready for output latching
APPLICATIONS
Multichannel, multimode receivers
AMPS, IS-136, CDMA, GSM, WCDMA
Single channel digital receivers
Antenna array processing
Communications instrumentation
Radar, infrared imaging
Instrumentation
GENERAL DESCRIPTION
The AD6644 is a high speed, high performance, monolithic 14-bit
analog-to-digital converter (ADC). All necessary functions,
including track-and-hold (TH) and reference, are included on-
chip to provide a complete conversion solution. The AD6644
provides CMOS-compatible digital outputs. It is the third
generation in a wideband ADC family, preceded by the AD9042
(12-bit 41 MSPS) and the AD6640 (12-bit 65 MSPS, IF
sampling).
AV
CC
AIN
TH1
A1
AIN
V
2.4V
REF
ENCODE
INTERNAL
TIMING
ENCODE
GND
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Analog-to-Digital Converter
Designed for multichannel, multimode receivers, the AD6644
is part of the Analog Devices, Inc. new SoftCell® transceiver
chipset. The AD6644 achieves 100 dB multitone, spurious-free
dynamic range (SFDR) through the Nyquist band. This break-
through performance eases the burden placed on multimode
digital receivers (software radios) which are typically limited by
the ADC. Noise performance is exceptional; typical signal-to-
noise ratio is 74 dB.
The AD6644 is also useful in single channel digital receivers
designed for use in wide-channel bandwidth systems (CDMA,
WCDMA). With oversampling, harmonics can be placed
outside the analysis bandwidth. Oversampling also facilitates
the use of decimation receivers (such as the AD6620), allowing
the noise floor in the analysis bandwidth to be reduced. By
replacing traditional analog filters with predictable digital
components, modern receivers can be built using fewer RF
components, resulting in decreased manufacturing costs, higher
manufacturing yields, and improved reliability.
The AD6644 is built on the Analog Devices high speed
complementary bipolar process (XFCB) and uses an innovative,
multipass circuit architecture. Units are packaged in a 52-lead
plastic low profile quad flat package (LQFP) specified from –
25°C to +85°C.
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate is 65 MSPS.
2. Fully differential analog input stage.
3. Digital outputs can be run on 3.3 V supply for easy interface
to digital ASICs.
4. Complete solution: reference and track-and-hold.
5. Packaged in small, surface-mount, plastic, 52-lead LQFP.
FUNCTIONAL BLOCK DIAGRAM
DV
CC
TH2
TH3
TH4
A2
ADC1
DAC1
ADC2
5
DIGITAL ERROR CORRECTION LOGIC
DMID OVR DRY D13
D12 D11 D10 D9
D8
(MSB)
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
14-Bit, 40 MSPS/65 MSPS
TH5
ADC3
6
DAC2
AD6644
5
D7
D6
D5
D4
D3
D2
D1
D0
(LSB)
©2007 Analog Devices, Inc. All rights reserved.
AD6644
www.analog.com

AD6644 Summary of contents

  • Page 1

    ... RF components, resulting in decreased manufacturing costs, higher manufacturing yields, and improved reliability. The AD6644 is built on the Analog Devices high speed complementary bipolar process (XFCB) and uses an innovative, multipass circuit architecture. Units are packaged in a 52-lead plastic low profile quad flat package (LQFP) specified from – ...

  • Page 2

    ... Edits to Specifications ...................................................................... 2 Renumbering of Figures and TPCs ..................................Universal Updated Outline Dimensions ....................................................... 19 Explanation of Test Levels............................................................7 Thermal Resistance .......................................................................7 ESD Caution...................................................................................7 Pin Configuration and Function Descriptions..............................8 Typical Performance Characteristics ..............................................9 Equivalent Circuits......................................................................... 12 Terminology .................................................................................... 13 Theory of Operation ...................................................................... 15 Applying the AD6644 ................................................................ 15 Evaluation Board ............................................................................ 18 Outline Dimensions ....................................................................... 21 Ordering Guide .......................................................................... 21 Rev Page ...

  • Page 3

    ... Rev Page AD6644AST-65 Max Min Typ 14 Guaranteed +10 −10 +3 +10 −10 –6 +1.5 −1.0 ±0.25 ±0. ±1.0 2.4 2 1.5 5.25 4.85 5.0 3.6 3.0 3.3 276 245 36 30 1.5 1 AD6644 Unit Max Bits + +1.5 LSB LSB ppm/°C ppm/°C mV p-p kΩ pF 5.25 V 3.6 V 276 1.5 W ...

  • Page 4

    ... Rev Page AD6644AST-65 Typ Max Min Typ 0 2.5 2.5 CMOS CMOS 2.5 2.5 0.4 0.4 Twos complement –25° +85°C, unless otherwise noted. MIN MAX AD6644AST-65 Typ Max Min Typ Max 6.5 6.5 = −25° +85°C, C MIN MAX LOAD AD6644AST-40/65 1 Min Typ 15.4 25 6.2 7.7 6.2 7.7 2.6 3.4 ...

  • Page 5

    ... Max Min Typ 74.5 74.5 74.0 72 74.0 73.5 72 73.5 74.5 74.5 74.0 72 74.0 73.0 73 100 100 90 90 250 250 AD6644 Unit Max 9.4 ns 14.2 ns 6 rms and t for a H_DR S_DR Unit Max dBc dBc dBc dBc dBc dBc dBFS dBc MHz ...

  • Page 6

    ... AD6644 TIMING DIAGRAM AIN ENCODE, ENCODE t E_RL D[13:0], OVR DRY ENCH ENCL t ENC E_FL E_DR N – – – S_DR t DR Figure 2. Timing Diagram Rev Page S_E ...

  • Page 7

    ... The following measurements were taken on a 6-layer board in 150°C still air with a solid ground plane. 300°C −65°C to +150°C Table 7. Thermal Resistance Package Type 52-lead LQFP ESD CAUTION Rev Page AD6644 θ θ Unit °C/W ...

  • Page 8

    ... PIN 1 GND 2 IDENTIFIER V 3 REF GND 4 ENCODE 5 ENCODE AD6644 6 TOP VIEW GND 7 (Not to Scale GND 10 AIN 11 AIN 12 GND Figure 3. Pin Configuration Mnemonic Description DV 3.3 V Power Supply (Digital), Output Stage Only. ...

  • Page 9

    ... TEMP = –25°C, +25°C, +85° +25° –25°C, +85° ANALOG INPUT FREQUENCY (MHz) LOW NOISE ANALOG SOURCE PHASE NOISE OF ANALOG SOURCE DEGRADES PERFORMANCE AIN = –1dBFS ENCODE = 65MSPS ANALOG FREQUENCY (MHz) Figure 9. Noise vs. Analog Frequency (IF) AD6644 30 30 100 ...

  • Page 10

    ... AD6644 100 ENCODE = 65MSPS 95 WORST OTHER SPUR AIN = –1dBFS HARMONICS (SECOND, THIRD ANALOG FREQUENCY (MHz) Figure 10. Harmonics vs. Analog Frequency (IF) 120 110 100 ENCODE = 65MSPS 90 AIN = 15.5MHz –80 –70 –60 –50 – ...

  • Page 11

    ... ENCODE = 65MSPS 90 AIN = 15.5MHz DITHER = –19dBm –90 –80 Rev Page AD6644 2.2MHz ENCODE = 65MSPS 30.5MHz SNR 2.2MHz 30.5MHz –10 – ENCODE INPUT POWER (dBm FREQUENCY (MHz) Figure 19. 1M FFT with Dither ...

  • Page 12

    ... AD6644 EQUIVALENT CIRCUITS AIN BUF 500Ω BUF 500Ω AIN BUF V CL Figure 21. Analog Input Stage LOADS 10kΩ ENCODE 10kΩ LOADS Figure 22. ENCODE/ ENCODE Inputs REF CURRENT MIRROR Figure 23 ...

  • Page 13

    ... Rev Page − ⎛ FS SNR = × × ⎜ dBm dBc 001 10 NOISE ⎝ 10 includes both thermal and quantization noise. AD6644 − ⎞ Signal ⎟ dBFS ⎠ ...

  • Page 14

    ... AD6644 Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. Reported in either dBc (that is, degrades as signal level is lowered), or dBFS (always related back to converter full scale). ...

  • Page 15

    ... In addition, they provide good rejection of common-mode signals such as local oscillator feedthrough. The AD6644 input voltage range is offset from ground by 2.4 V. Each analog input connects through a 500 Ω resistor to a 2.4 V bias voltage and to the input of a differential buffer (Figure 21). ...

  • Page 16

    ... A full-scale transition can cause up to 140 mA (14 bits × 10 mA/bit) of current to flow through the output stages. The series resistors should be placed as close as possible to the AD6644 to limit the amount of current that can flow into the output stage. These switching currents are confined between ground and the DV because they can appreciably add to the dynamic switching currents of the AD6644 ...

  • Page 17

    ... V rms thermal noise referred to the analog input NOISE rms of the ADC (typically 2.5 LSB). For a 14-bit ADC like the AD6644, aperture jitter can greatly affect the SNR performance as the analog frequency is increased. Figure 31 shows a family of curves that demonstrates the expected SNR performance of the AD6644 as jitter increases and is derived from Equation 1 ...

  • Page 18

    ... AD6644, minimal capacitive loading should be placed on these outputs recommended that a fanout of only one gate should be used for all AD6644 digital outputs. The layout of the encode circuit is equally critical. Any noise received on this circuitry results in corruption in the digitization process and lower overall performance ...

  • Page 19

    ... D4 C AVC +3P3V C DVC AVC D10 C AVC D11 D GN D12 C AVC D13 _OU AVC 0.0 Figure 32. Evaluation Board Schematic Rev Page AD6644 00971-032 A +5V A +5V A +5V A +5V A +5V 0.0 ...

  • Page 20

    ... AD6644 Figure 33. Top Signal Level Figure 34. 5.0 V Plane Layer 3 and 3.3 V Plane Layer 4 Figure 35. Ground Plane Layer 2 and Ground Plane Layer 5 Figure 36. Bottom Signal Layer Rev Page ...

  • Page 21

    ... Low Profile Quad Flat Package (LQFP) 52-Lead Low Profile Quad Flat Package (LQFP) 52-Lead Low Profile Quad Flat Package (LQFP) 52-Lead Low Profile Quad Flat Package (LQFP) Evaluation Board with AD6644AST–65 Evaluation Board with AD6644AST–65 Rev Page AD6644 ...

  • Page 22

    ... AD6644 NOTES Rev Page ...

  • Page 23

    ... NOTES Rev Page AD6644 ...

  • Page 24

    ... AD6644 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00971-0-8/07(D) Rev Page ...