AD7472 Analog Devices, AD7472 Datasheet - Page 10

• Manufacturer Part Number: AD7472
• Description: 12-Bit, 2.7 V to 5.25 V, 1.5 MSPS Low Power ADC
• Manufacturer: Analog Devices

Specifications of AD7472

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 1.5MSPS
• Interface: Par
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: SOIC,SOP

AD7470/AD7472
CIRCUIT DESCRIPTION
CONVERTER OPERATION
The AD7470/AD7472 are 10-bit/12-bit successive approxima-
tion analog-to-digital converters based around a capacitive
DAC. The AD7470/AD7472 can convert analog input signals in
the range 0 V to V
matic of the ADC. The control logic, SAR, and the capacitive
DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator back into a
balanced condition.
Figure 3 shows the ADC during its acquisition phase. SW2 is
closed and SW1 is in Position A. The comparator is held in a
balanced condition and the sampling capacitor acquires the
signal on V
Figure 4 shows the ADC during conversion. When conversion
starts, SW2 will open and SW1 will move to position B, causing
the comparator to become unbalanced. The ADC then runs
through its successive approximation routine and brings the
comparator back into a balanced condition. When the compara-
tor is rebalanced, the conversion result is available in the SAR
register.
Figure 2. Simplified Block Diagram of AD7470/AD7472
AGND
AGND
CONTROL
V
V
INPUTS
IN
IN
V
REF
V
IN
IN
SW1
SW1
A
A
.
Figure 4. ADC Conversion Phase
Figure 3. ADC Acquisition Phase
B
B
CAPACITIVE
SWITCHES
REF
DAC
SAR
. Figure 2 shows a very simplified sche-
CONTROL LOGIC
2k
2k
SW2
SW2
COMPARATOR
COMPARATOR
COMPARATOR
OUTPUT DATA
10-/12-BIT PARALLEL
CONTROL LOGIC
CONTROL LOGIC
CAPACITIVE
CAPACITIVE
DAC
DAC
–10–
TYPICAL CONNECTION DIAGRAM
Figure 5 shows a typical connection diagram for the AD7470/
AD7472. Conversion is initiated by a falling edge on CONVST.
Once CONVST goes low, the BUSY signal goes high, and at
the end of conversion, the falling edge of BUSY is used to acti-
vate an interrupt service routine. The CS and RD lines are then
activated in parallel to read the 10- or 12-data bits. The recom-
mended REF IN voltage is 2.5 V providing an analog input
range of 0 V to 2.5 V, making the AD7470/AD7472 a unipolar
ADC. It is recommended to perform a dummy conversion after
power-up as the first conversion result could be incorrect. This
also ensures that the part is in the correct mode of operation.
The CONVST pin should not be floating when power is applied
as a rising edge on CONVST might not wake up the part.
In Figure 5 the V
output voltage values being either 0 V or DV
applied to V
signals. For example, if DV
V
either 0 V or 3 V. This feature allows the AD7470/AD7472 to
interface to 3 V parts while still enabling the ADC to process
signals at 5 V supply.
*RECOMMENDED REF IN VOLTAGE
DRIVE
C/ P
by a 3 V supply, the logic output voltage levels would be
Figure 5. Typical Connection Diagram
DRIVE
2.5V*
0.1 F
INTERFACE
PARALLED
DRIVE
controls the voltage value of the output logic
1nF
pin is tied to DV
10 F
DD
10 F
V
DV
REF IN
DB0–
DB9 (DB11)
CS
CONVST
RD
BUSY
is supplied by a 5 V supply and
DRIVE
DD
AD7470/
AD7472
+
AV
DD
DD
V
0.1 F
IN
, which results in logic
DD
+
. The voltage
0V TO
REF IN
47 F
ANALOG
SUPPLY
2.7V–5.25V
REV. B