AD7723 Analog Devices, AD7723 Datasheet
AD7723
Specifications of AD7723
Available stocks
Related parts for AD7723
AD7723 Summary of contents
Page 1
... A power-down mode reduces the idle power consumption to 200 µW. The AD7723 is available in a 44-lead MQFP package and is specified over the industrial temperature range from –40°C to +85°C. Two input modes are provided, allowing both unipolar and bipolar input ranges ...
Page 2
... Data Interfacing .............................................................................. 24 Parallel Interface......................................................................... 24 Serial Interface ................................................................................ 25 Two-Channel Multiplexed Operation ..................................... 25 Serial Interface to DSPs ................................................................. 27 AD7723 to ADSP-21xx Interface ............................................. 27 AD7723 to SHARC Interface.................................................... 27 AD7723 to DSP56002 Interface ............................................... 27 AD7723 to TMS320C5x Interface............................................ 27 Grounding and Layout .................................................................. 28 Outline Dimensions ....................................................................... 29 Ordering Guide .......................................................................... 29 9/02—Data Sheet changed from Rev Rev. A New TPCs 1 and 2 Added ............................................................. 13 Edits to Figures 17 and 18 ...
Page 3
... V reference Measurement bandwidth = 0.383 × 2.5 V reference 3 V reference Measurement bandwidth = 0.5 × 2.5 V reference 3 V reference 2.5 V reference 3 V reference Measurement bandwidth = 0.383 × Measurement bandwidth = 0.5 × Rev Page AD7723 = unless A MIN MAX B Version Min Typ Max 87 90 88.5 91 86.5 89 − ...
Page 4
... AD7723 Parameter Low-Pass Decimate kHz to f /41.75 CLKIN f /33.45 CLKIN f /32 CLKIN f /25. CLKIN CLKIN Group Delay Settling Time Band-Pass Decimate /51. /41.75 CLKIN CLKIN f /62.95, f /33.34 CLKIN CLKIN f /64, f /32 CLKIN CLKIN 0 kHz to f /83.5, f /25. CLKIN CLKIN CLKIN Group Delay Settling Time ...
Page 5
... Test Conditions/Comments | 200 µA OUT | 1.6 mA OUT HALF_PWR = Logic Low HALF_PWR = Logic High HALF_PWR = Logic Low HALF_PWR = Logic High Standby Mode in decimate by 16 mode and from dc to 0.0120 × f CLKIN . DD Rev Page AD7723 B Version Min Typ Max 4.0 0.4 4.75 5. 4.75 5. ...
Page 6
... AD7723 TIMING SPECIFICATIONS ± 5%; AGND = AGND1 = DGND = high unless otherwise noted. A MIN MAX Table 2. Parameter CLKIN Frequency CLKIN Period (t – 1/f ) CLK CLK CLKIN Low Pulse Width CLKIN High Pulse Width CLKIN Rise Time CLKIN Fall Time ...
Page 7
... Figure 5. Serial Mode 2: Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output, and Serial Data Output (See Table 3 for Control Inputs, TSI = DOE CLKIN CYCLES D14 D13 CLKIN CYCLES t 12 D14 D13 D12 D11 D5 Rev Page D15 D14 D15 D14 D4 AD7723 ...
Page 8
... AD7723 CLKIN t 8 FSI t 14 SCO (CFMT = FSO D15 D14 SDO D2 D1 Figure 6. Serial Mode 3: Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output, and Serial Data Output (See Table 3 for Control Inputs, TSI = DOE) Table 3. Serial Interface (MODE1 = 0, MODE2 = 0) ...
Page 9
... Figure 8. Parallel Mode Read Timing, CS and RD Tied Logic Low CLKIN DRDY t 22 RD/ DB0–DB15 CLKIN t 26 SYNC t 25 DRDY WORD VALID DATA t 23 Figure 9. Parallel Mode Read Timing Figure 10. SYNC Timing Rev Page AD7723 WORD ...
Page 10
... AD7723 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 5. Parameter Rating DV to DGND −0 AGND −0 DD1 − DD1 DD AGND, AGND1 to DGND −0 +0.3 V Digital Inputs to DGND −0 Digital Outputs to DGND − ...
Page 11
... Analog Input Range Select Input. The UNI pin selects the analog input range for either bipolar or unipolar operation. A logic high input selects unipolar operation and a logic low selects bipolar operation. 27 STBY Standby Logic Input. A logic high sets the AD7723 into the power-down state ...
Page 12
... SYNC allows each ADC to simultaneously sample its analog input and update its output register. A rising edge resets the AD7723 digital filter sequencer counter to 0. When the rising edge of CLKIN senses a logic low on SYNC, the reset state is released. Because the digital filter and sequencer are completely reset during this action, SYNC pulses cannot be applied continuously ...
Page 13
... Time Slot Logic Input. The logic level on TSI sets the active state of the DOE pin. With TSI set logic high, DOE enables the SDO output buffer when logic high and vice versa. TSI is used when two AD7723s are connected to the same serial data bus ...
Page 14
... The frequency above which the AD7723’s frequency response will be within its stop-band attenuation. Stop-Band Attenuation The AD7723’s frequency response will not have less than attenuation in the stated frequency band. Integral Nonlinearity This is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function ...
Page 15
... INPUT SIGNAL = 10kHz 94 MEASUREMENT BANDWIDTH = 0.383 × OWR 100 500 1000 1500 OUTPUT WORD RATE (kHz) INPUT SIGNAL = 10kHz MEASUREMENT BANDWIDTH = 0.5 × OWR SFDR THD 95 SNR 90 50 150 300 450 600 OUTPUT WORD RATE (kHz) AD7723 75 100 SNR 2150 750 900 ...
Page 16
... SOURCE 1µF × (R )/(2 × BALANCE2 IN SOURCE FB × )/R IN SOURCE FB 67108864 SAMPLES TAKEN DIFFERENTIAL MODE 0 16384 32768 49152 CODE 67108864 SAMPLES TAKEN DIFFERENTIAL MODE 0 16384 32768 49152 CODE VIN(+) AD7723 VIN(–) REF2 REF1 65535 65535 ...
Page 17
... Figure 26 Point FFT (Output Data Rate = 600 kHz) 500k 600k Rev Page AD7723 SNR = –89.91dB SNR + D = –89.7dB THD = –101.16dB SFDR = –102.1dB 2ND HARMONIC = –102.1dB 3RD HARMONIC = –110.3dB A = 50kHz IN MEASURED BW = 300kHz 150k ...
Page 18
... CLKIN CLKIN state on the MODE1/MODE2 pins in parallel interface mode or the SLDR pin in serial interface mode. The AD7723 output data rate is a little over twice the signal bandwidth, which guarantees that there is no loss of data in the signal band. Digital filtering has certain advantages over analog filtering. ...
Page 19
... Out-of-band noise or signals coincident with CLKIN any of the filter images are aliased down to the pass band. However, due to the AD7723’s high oversampling ratio, these bands occupy only a small fraction of the spectrum, and most broadband noise is attenuated by at least 90 dB. In addition, as shown in Figure 33, with even a low-order filter, there is significant attenuation at the first image frequency ...
Page 20
... DRIVING THE ANALOG INPUTS (+8/5 × V – 1LSB) UNIPOLAR REF2 To interface the signal source to the AD7723, at least one op amp is generally required. Choice of op amp is critical to achieving the full performance of the AD7723. The op amp not only has to recover from the transient loads that the ADC imposes on it, but it must also have good distortion characteristics and very low input noise ...
Page 21
... Figure 38 and Figure 39 show two such circuits for driving the AD7723. Figure 38 is intended for use when the input signal is biased about 2.5 V, while Figure 39 is used when the input signal is biased about ground. While both circuits convert the input signal into a complementary signal, the circuit in Figure 39 also level shifts the signal so that both outputs are biased about 2 ...
Page 22
... AD7723 digital ground plane. If the clock signal is passed between its 10nF origin on a digital ground plane to the AD7723 on the analog REF1 ground plane, the ground noise between the two planes adds directly to the clock and produces excess jitter. The jitter can cause degradation in the signal-to-noise ratio and also produce unwanted harmonics ...
Page 23
... This allows a system using multiple AD7723s, operated from a common master clock synchronized so that each ADC simultaneously updates its output register system using multiple AD7723s, a common signal to their sync inputs synchronizes their operation. On the rising edge of SYNC, the digital filter sequencer is reset to 0. The filter is held in a reset state until a rising edge on CLKIN senses SYNC low ...
Page 24
... PARALLEL INTERFACE When using the AD7723, place a buffer/latch adjacent to the converter to isolate the converter’s data lines from any noise that may be on the data bus. Even though the AD7723 has three state outputs, use of an isolation latch represents good design practice. ...
Page 25
... SFMT, FSO goes low at the beginning of a data transmission frame and returns high after 16 SCO cycles. Note that in Serial Mode 1, FSI can be used to synchronize the AD7723 if SFMT is set to a logic high. If SFMT is set low, the FSI input has no effect on synchronization. In Serial Mode 2 and Serial Mode 3, SFMT should be tied high. ...
Page 26
... AD7723 The master device is selected by setting TSI to a logic low and connecting its FSO to DOE. The slave device is selected with its TSI pin tied high and both its FSI and DOE controlled from the master’s FSO. Since the FSO of the master controls the DOE input of both the master and slave, one ADC’ ...
Page 27
... DSP begins reading the 16-bit word after the DSP has identified the frame sync signal rather than the DSP reading the word at the same instant as the frame sync signal is identified), and LRFS = 0 (RFS is active high). The AD7723 can be used in Mode 1, Mode 2, or Mode 3 when interfaced to the ADSP- 2106x SHARC DSP. ...
Page 28
... The analog ground plane should be allowed to run under the AD7723 to shield it from noise coupling. The power supply lines to the AD7723 should use as large a trace as possible (preferably a plane) to provide a low impedance path and reduce the effects of glitches on the power supply line. ...
Page 29
... MIN VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Package AD7723BS –40°C to +85°C AD7723BS-REEL –40°C to +85°C 1 AD7723BSZ –40°C to +85°C 1 AD7723BSZ-REEL –40°C to +85°C EVAL-AD7723CB Pb-free part. 1.03 2.45 MAX 0.88 0.73 33 SEATING 34 PLANE 0.23 VIEW A 0.11 7° 44 0° ...
Page 30
... AD7723 NOTES Rev Page ...
Page 31
... NOTES Rev Page AD7723 ...
Page 32
... AD7723 NOTES ©2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01186–0–5/05(C) Rev Page ...