AD9224 Analog Devices, AD9224 Datasheet
AD9224
Specifications of AD9224
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AD9224 Summary of contents
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... The input of the AD9224 allows for easy interfacing to both imaging and communications systems. With a truly differential input structure, the user can select a variety of input ranges and offsets, including single-ended applications ...
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... Supply Current IAVDD IDRVDD POWER CONSUMPTION NOTES 1 Includes internal voltage reference error. 2 Excludes internal voltage reference error. 3 Load regulation with 1 mA load current (in addition to that required by the AD9224). Specifications subject to change without notice MSPS, VREF = 2.0 V, VINB = 2.5 V dc, T SAMPLE Min Typ Max 12 40 0.35 ...
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... Min Typ Max +3.5 +1.0 –10 +10 –10 +10 5 +4.5 +2.4 +0.4 +0.1 5 +2.95 +2.80 +0.4 +0. pF) L Min Typ Max 25 12.37 12. AD9224 Units MHz MHz ns ps rms Units Units Clock Cycles ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9224 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. SPURIOUS FREE DYNAMIC RANGE (SFDR) SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal. –5– AD9224 ...
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... AD9224 Typical Performance Characteristics 1.00 0.75 0.50 0.25 0.00 –0.25 –0.50 –0.75 –1.00 0 511 1022 1533 2044 2555 CODE Title Figure 2. Typical DNL 75 70 –0.5dB 65 –6.0dB 60 55 –20.0dB 0 INPUT FREQUENCY – MHz Figure 3. SINAD vs. Input Frequency (Input Span = 4 ...
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... Figure 12. +SNR/–THD vs. Input Frequency (F Input Span = 4.0 V p-p, V 2857 N+1 –7– SAMPLE RATE – MHz = –0.5 dB 2.5 V Differential Input) CM THD SNR 0 0 INPUT FREQUENCY = 2.5 V Differential Input) CM AD9224 MHz, S ...
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... The output drivers of the AD9224 can be configured to interface with + +3.3 V logic families. The AD9224 uses both edges of the clock in its internal timing circuitry (see Figure 1 and specification page for exact timing requirements). The A/D samples the analog input on the rising edge of the clock input ...
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... ON S1 tance of the AD9224, a lower series resistance can be selected to establish the filter’s cutoff frequency while not degrading the distortion performance of the device. The shunt capacitance also acts like a charge reservoir, sinking or sourcing the addi- tional charge required by the hold capacitor, C ing current transients seen at the op amp’ ...
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... A1 Figure 16. Equivalent Reference Circuit The actual reference voltages used by the internal circuitry of the AD9224 appear on the CAPT and CAPB pins. For proper operation when using the internal or an external reference necessary to add a capacitor network to decouple these pins. Figure 17 shows the recommended decoupling network. This ...
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... Optimum noise performance. Table II. Reference Configuration Summary Required VREF ( VREF 2.0 AND VREF = (1 + R1/R2) 1 VREF 2.0 CAPT and CAPB Externally Driven –11– AD9224 Connect To SENSE VREF SENSE REFCOM R1 VREF AND SENSE R2 SENSE AND REFCOM SENSE AVDD VREF EXT. REF. ...
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... Figure 24. Single-ended operation requires that VINA coupled to the input signal source, while VINB of the AD9224 be biased to the appropriate voltage corresponding to a midscale code transi- tion. Note that signal inversion may be easily accomplished by transposing VINA and VINB ...
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... V/–5 V operation and/ or specified for +5 V single-supply operation can be easily to 100 connected to configured for the input span of the AD9224. A differential input connection should be considered for opti- mum ac performance. Simple AC Interface Figure 21 shows a typical example of an ac-coupled, single- ended configuration ...
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... Nyquist frequency (i.e., f The circuit shown in Figure ideal method of applying a differential dc drive to the AD9224. We have used this configu- ration to drive the AD9224 from spans at frequencies approaching Nyquist, with performance numbers matching those shown on the Specification pages of this data sheet (gath- ered through a transformer) ...
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... THD and SNR performance of the A/D. R help provide a low-pass filter to block high frequency noise. The AD9224 can be easily configured for either p-p input span or 4.0 V p-p input span by setting the internal reference (see Table II). Other input spans can be realized with two exter- nal gain setting resistors as shown in Figure 28 of this data sheet. Figure 25a demonstrates the AD9224’ ...
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... Figure 17. USING THE INTERNAL REFERENCE Single-Ended Input with VREF Range Figure 26a shows how to connect the AD9224 for input range via pin strapping the SENSE pin. An intermediate input range VREF can be established using the resistor programmable configuration in Figure 28 ...
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... REF191, a 2.048 V external reference was selected, the valid input range extends from 0 to 4.096 V. In this case, 1 LSB of the AD9224 corresponds essential that a mini- mum capacitor in parallel with a 0.1 F low inductance ceramic capacitor decouple the reference output to ground. ...
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... V CMOS logic levels. This can also be accomplished by ac-coupling and level-shifting the clock signal. The AD9224 has a very tight clock tolerance at 40 MHz. One way to minimize the tolerance of a 50% duty cycle clock is to Analog Input Is divide down a clock of higher frequency, as shown in Figure 33 ...
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... AD9224 is capable of still maintaining 64 SNR MHz with input span. Note, although the AD9224 can yield improvement in SNR when configured for the larger 4 V span, the 2 V span achieves the optimum full- scale distortion performance at these higher input frequencies ...
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... The performance characteristics in these figures are representative of the AD9224 without any preceding gain stage. The AD9224 was operated in the differential mode (via transformer) with span and a sample rate between 28 MSPS and 36 MSPS. The analog supply (AVDD) and the digital supply (DRVDD) were set and +3 ...
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... Note that the AVDD and AVSS pins are colocated on the AD9224 to simplify the layout of the decoupling capacitors and provide the shortest possible PCB trace lengths. The AD9224/AD9225EB power plane layout, shown in Figure 48 depicts a typical arrangement using a multi- layer PCB ...
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... VINA VINB C32 AVSS1 0.1 F AVDD1 DRVSS DRVDD CLK 1 C24 AD9224 0 DUTDRVDD 1 1 C37 C40 0.1 F 0.001 C42 15pF C41 C38 1 0.001 F 0.1 F C43 2 2 15pF 2 L6 TP40 TP5 FBEAD ...
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... Figure 46. Evaluation Board Ground Plane Layout (Not to Scale) Figure 47. Evaluation Board Component Side Silkscreen (Not to Scale) REV. A Figure 48. Evaluation Board Solder Side Layout (Not to Scale) Figure 49. Evaluation Board Power Plane Layout Figure 50. Evaluation Board Solder Side Silkscreen (Not to Scale) –23– AD9224 ...
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... AD9224 0.078 (1.98) 0.068 (1.73) 0.008 (0.203) 0.002 (0.050) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Shrink Small Outline (SSOP) (RS-28) 0.407 (10.34) 0.397 (10.08 0.07 (1.79) PIN 1 0.066 (1.67) 8° 0.0256 0.015 (0.38) 0° SEATING 0.009 (0.229) (0.65) 0.010 (0.25) PLANE BSC 0.005 (0.127) –24– 0.03 (0.762) 0.022 (0.558) ...