AD9225 Analog Devices, AD9225 Datasheet
AD9225
Specifications of AD9225
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AD9225 Summary of contents
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... The input of the AD9225 allows for easy interfacing to both imaging and communications systems. With the device’s truly differential input structure, the user can select a variety of input ranges and offsets, including single-ended applications ...
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... POWER CONSUMPTION External Reference Internal Reference NOTES 1 Includes internal voltage reference error. 2 Excludes internal voltage reference error. 3 Load regulation with 1 mA load current (in addition to that required by the AD9225). Specifications subject to change without notice MSPS, VREF = 2.0 V, VINB = 2.5 V dc, T SAMPLE Min Typ Max 12 25 ...
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... with AVDD = 5 V, DRVDD = MIN MAX Symbol Min –3– AD9225 Differential Input unless MIN MAX Max Unit –72 dB –71 MHz MHz ns ps rms ns Typ Max Unit V 1 ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9225 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal. –5– AD9225 N = (SINAD – 1.76)/6.02 ...
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... AD9225–Typical Performance Characteristics (AVDD, DRVDD = MHz (50% Duty Cycle), unless otherwise noted.) S 1.00 0.75 0.50 0.25 0.00 –0.25 –0.50 –0.75 –1.00 0 511 1022 1533 2044 2555 Title TPC 1. Typical DNL 75 0.5dB 2V INT REF 70 6dB 2V INT REF 20dB 2V INT REF 50 1 FREQUENCY (MHz) TPC 2. SINAD vs. Input Frequency (Input Span = 4 ...
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... TPC 11. SNR vs. Input Frequency (Input Span = 4.0 V p-p, V 4206 –7– –70 –75 –80 INT 1V REF –85 INT 2V REF –90 10 FREQUENCY (MHz) = –0.5 dB 2.5 V, Input Span = 4.0 V p-p Differential Input) 75 0.5dB 2V INT REF 70 6.0dB 2V INT REF 20.0dB 2V INT REF FREQUENCY (MHz) = 2.5 V Single-Ended Input) CM AD9225 ...
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... The digital output, together with the out-of-range indicator (OTR), is latched into an output buffer to drive the output pins. The output drivers of the AD9225 can be configured to interface with 3.3 V logic families. The AD9225 uses both edges of the clock in its internal timing circuitry (see Figure 1 and Specifications tables for exact timing requirements) ...
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... VINA and/or VINB) and analog ground. Since this additional shunt capacitance combines with the equivalent input capaci- tance of the AD9225, a lower series resistance can be selected to of switch establish the filter’ ...
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... V and 2 V. Another alternative is to use an external reference for designs requiring enhanced accuracy and/or drift performance. See Table II for a summary of the pin strapping options for the AD9225 refer- ence configurations. Figure 5 shows a simplified model of the internal voltage reference of the AD9225 ...
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... THD and SFDR performance can be traded off for better noise performance. 12, 13 Optimum noise performance. Connect To SENSE VREF SENSE REFCOM R1 VREF and SENSE R2 SENSE and REFCOM SENSE AVDD VREF External Reference SENSE AVDD VREF AVSS External Reference CAPT External Reference CAPB AD9225 ...
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... AD9225 input to provide a filter pole. Simple Op Amp Buffer the simplest case, the input signal to the AD9225 will already be 20 AD9225 biased at levels in accordance with the selected input range simply necessary to provide an adequately low source impedance for the VINA and VINB analog pins of the ADC ...
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... VINA and VINB are biased to midsupply independent of VREF, VREF can be pin strapped or reconfigured to achieve input spans between 2 V and 4 V p-p. The AD9225’s CMRR along with the symmetrical coupling R-C networks will reject both power supply variations and noise. The resistors, R, establish the common-mode ...
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... AD8056 Dual Op Amp The circuit shown in Figure ideal method of applying a differential dc drive to the AD9225. We have used this configura- tion to drive the AD9225 from spans at frequencies approaching Nyquist with performance numbers matching those listed in the Specifications tables (gathered through a transformer). ...
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... C help provide a low-pass filter to block high frequency noise. S The AD9225 can be easily configured for either p-p input span or a 4.0 V p-p input span by setting the internal reference (see Table II). Other input spans can be realized with two external gain setting resistors as shown in Figure 19. Figures 14 and 15 demon- ...
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... USING THE INTERNAL REFERENCE Single-Ended Input with VREF Range Figure 16 shows how to connect the AD9225 for input range via pin strapping the SENSE pin. An inter- mediate input range ¥ VREF can be established using the resistor programmable configuration in Figure 19 ...
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... VREF. For example, if the REF191, a 2.048 V exter- nal reference was selected, the valid input range extends from 0 to 4.096 V. In this case, 1 LSB of the AD9225 corresponds essential that a minimum capacitor in parallel with a 0.1 mF low inductance ceramic capacitor decouple the reference output to ground ...
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... V CMOS logic levels. This can also be accomplished by ac coupling and level-shifting the clock signal. The AD9225 has a clock tolerance MHz. One way to obtain a 50% duty cycle clock is to divide down a clock of higher frequency, as shown in Figure 24. This configuration will also decrease the jitter of the source clock. OVER = “ ...
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... SNR degradation at higher IF frequencies. In fact, the AD9225 is capable of still maintaining SNR MHz with input span. Although the AD9225 can yield improvement in SNR when configured for the larger 4 V span, the 2 V span achieves the optimum full-scale distor- tion performance at these higher input frequencies ...
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... Figure 39 depicts a typical arrangement using a multi- layer PCB. The CML is an internal analog bias point used internally by the AD9225. This pin must be decoupled with at least a 0.1 mF capacitor as shown in Figure 33. The dc level of CML is approximately AVDD/2. This voltage should be buffered used for any external biasing. ...
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... The digital activity on the AD9225 chip falls into two general categories: correction logic and output drivers. The internal correction logic draws relatively small surges of current, mainly during the clock transitions. The output drivers draw large current impulses while the output bits are changing. The size and duration of these currents are a function of the load on the output bits ...
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... CML VINA VINB C32 AVSS1 0.1 F AVDD1 DRVSS DRVDD CLK 1 AD9225 C24 0 DUTDRVDD 1 1 C37 C40 0.1 F 0.001 C42 15pF C41 C38 1 0.001 F 0.1 F C43 2 2 15pF 2 L6 TP40 TP5 ...
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... Figure 37. Evaluation Board Ground Plane Layout (Not to Scale) Figure 38. Evaluation Board Component Side Silkscreen (Not to Scale) Rev. C Figure 39. Evaluation Board Solder Side Layout (Not to Scale) Figure 40. Evaluation Board Power Plane Layout Figure 41. Evaluation Board Solder Side Silkscreen (Not to Scale) –23– AD9225 ...
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... Temperature Range AD9225AR −40°C to +85°C AD9225ARS −40°C to +85°C AD9225ARSRL −40°C to +85°C AD9225ARZ −40°C to +85°C AD9225ARZRL −40°C to +85°C AD9225ARSZ −40°C to +85°C AD9225ARSZRL −40°C to +85° RoHS Compliant Part. 18.10 (0.7126) 17 ...
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... Moved and Changes to Ordering Guide ..................................... 24 8/03—REV REV. B Renumbered TPCs and Figures ........................................ Universal Changes to Ordering Guide ............................................................ 4 Updated Outline Dimensions ....................................................... 24 ©1998–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00577-0-1/11(C) Rev Page AD9225 ...