AD9240 Analog Devices, AD9240 Datasheet
AD9240
Specifications of AD9240
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AD9240 Summary of contents
Page 1
... The AD9240 offers a complete single-chip sampling 14-bit, analog-to-digital conversion function in a 44-lead Metric Quad Flatpack. Low Power and Single Supply The AD9240 consumes only 280 single +5 V power supply. Excellent DC Performance Over Temperature The AD9240 provides no missing codes, and excellent tempera- ture drift performance over the full operating temperature range ...
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... DVDD DRVDD Supply Current IAVDD IDRVDD IDVDD POWER CONSUMPTION NOTES 1 VREF = Including internal reference. 3 Excluding internal reference. 4 Load regulation with 1 mA load current (in addition to that required by the AD9240). Specification subject to change without notice. SAMPLE unless otherwise noted) MAX AD9240 14 10 0.9 0.36 2.5 0.6 1.0 2.5 0 ...
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... AD9240 +3.5 +1 +4.5 +2.4 +0.4 +0.1 5 +2.4 +0.7 AD9240 = –0.5 dBFS, IN Units dB min dB typ dB typ dB typ Bits min Bits typ Bits typ Bits typ dB min dB typ dB typ dB typ dB max dB typ dB typ dB typ dB typ dB typ dB typ MHz typ MHz typ ns typ ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9240 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. Two-tone SFDR may be reported in dBc (i.e., degrades as signal level is lowered dBFS (always related back to converter full scale). –5– AD9240 ...
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... AD9240 Typical Differential AC Characterization Curves/Plots –0.5dBFS 75 –6.0dBFS 70 65 –20.0dBFS 0 INPUT FREQUENCY – MHz Figure 2. SINAD vs. Input Frequency (Input Span = 2 –0.5dBFS 75 –6.0dBFS –20.0dBFS INPUT FREQUENCY – MHz Figure 5 ...
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... INPUT FREQUENCY – MHz Figure 18. THD vs. Input Frequency (Input Span = 2 –7– AD9240 = 10 MSPS SAMPLE BIAS 13484335 1414263 1482053 N–1 N N+1 CODE Figure 13. “Grounded-Input” Histogram (Input Span = –10 –20 – ...
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... The output drivers can be con- figured to interface with + +3.3 V logic families. The AD9240 uses both edges of the clock in its internal timing circuitry (see Figure 1 and specification page for exact timing requirements). The A/D samples the analog input on the rising edge of the clock input ...
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... PAR Figure 24. Simplified Input Circuit B REV. The input SHA of the AD9240 is optimized to meet the perfor- mance requirements for some of the most demanding commu- nication, imaging, and data acquisition applications while maintaining low power dissipation. Figure graph of the full-power bandwidth of the AD9240, typically 60 MHz. Note that the small signal bandwidth is the same as the full-power bandwidth ...
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... V input span) and matched input impedance for VINA and VINB. Note that only a slight degradation in dc linearity performance exists between the 2 V and 5 V input span as specified in the AD9240 DC SPECIFICATIONS. Referring to Figure 24, the differential SHA is implemented using a switched-capacitor topology ...
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... Widest dynamic range (i.e., ENOBs) due to optimum noise performance. Table II. Reference Configuration Summary Required VREF (V) 1 2.5 1 VREF 2.5 AND VREF = (1 + R1/R2) 1 VREF 2.5 CAPT and CAPB Externally Driven –11– AD9240 Connect To SENSE VREF SENSE REFCOM R1 VREF AND SENSE R2 SENSE AND REFCOM SENSE AVDD VREF EXT. REF. SENSE ...
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... A1 Figure 29. Equivalent Reference Circuit The actual reference voltages used by the internal circuitry of the AD9240 appear on the CAPT and CAPB pins. For proper operation when using the internal or an external reference necessary to add a capacitor network to decouple these pins. Figure 30 shows the recommended decoupling network. This ...
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... Direct IF to Digital Conversion). The dc- coupled differential mode of operation also provides an enhance- ment in distortion and noise performance at higher input spans. Furthermore, it allows the AD9240 to be configured for span using op amps specified for + operation. Single-ended operation requires that VINA coupled ...
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... DD specified for single supply +5 V operation since it will inherently limit its output swing to within the power supply rails. Rail-to- rail output amplifiers such as the AD8041 allow the AD9240 to be configured with larger input spans which improves the noise performance. –14– ...
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... If the application requires the largest single-ended input range (i.e the AD9240, the op amp will require larger supplies to drive it. Various high speed amplifiers in the Op Amp Selection Guide of this data sheet can be selected to accommodate a wide range of supply options. Once again, clamping the output of the amplifier should be considered for these applications ...
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... VINB Single-Ended Input with Figure 39 shows how to connect the AD9240 for input range via pin strapping the SENSE pin. An intermediate input range VREF can be established using the resistor programmable configuration in Figure 41 and connecting VREF to VINB ...
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... set at midsupply by connecting the transformer’s center CM tap to CML of the AD9240. VREF can be configured for 2 connecting SENSE to either VREF or REFCOM respectively. Note that the valid input range for each of the differential inputs is one half of the single-ended input and thus becomes V – ...
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... AD9240 Variable Input Span with Figure 42 shows an example of the AD9240 configured for an input span of 2 VREF centered at 2 external 2.5 V reference drives the VINB pin thus setting the common-mode voltage at 2.5 V. The input span can be independently set by a voltage divider consisting of R1 and R2, which generates the VREF signal ...
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... B REV. Most of the power dissipated by the AD9240 is from the analog power supply; however, lower clock speeds will reduce digital current slightly. Figure 47 shows the relationship between power and clock rate. ...
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... AVSS Figure 49. Analog Supply Decoupling The CML is an internal analog bias point used internally by the AD9240. This pin must be decoupled with at least a 0.1 F capacitor as shown in Figure 50. The dc level of CML is ap- proximately AVDD/2. This voltage should be buffered used for any external biasing. ...
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... T4-6T @ 37.45 MHz Figure 54 compares the two tone SFDR performance of the AD9240 in the 2 V span with and without the use of the AD8009 gain stage. No degradation in distortion performance was noted with the inclusion of the AD8009 gain stage provided that the AD8009 2nd order distortion products are sufficiently attenu- ated by the bandpass filter ...
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... AD9240 AVSS1 AVSS2 AVDD1 AVDD2 DVDD DRVDD DVSS DRVSS Figure 55. Evaluation Board Schematic –22– SJ5 SJ4 SJ3 SJ2 SJ1 JG1 REV. B ...
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... Figure 56. Evaluation Board Component Side Layout (Not to Scale) Figure 57. Evaluation Board Solder Side Layout (Not to Scale) B REV. Figure 58. Evaluation Board Ground Plane Layout (Not to Scale) Figure 59. Evaluation Board Power Plane Layout (Not to Scale) –23– AD9240 ...
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... AD9240AS −55°C to +85°C AD9240ASRL −55°C to +85°C AD9240ASZ −55°C to +85°C AD9240ASZRL −55°C to +85° RoHS Compliant Part. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...