AD7854 Analog Devices, AD7854 Datasheet - Page 20

• Manufacturer Part Number: AD7854
• Description: 3 V to 5 V Single Supply, 200 kSPS, 12-Bit, Parallel Sampling ADC
• Manufacturer: Analog Devices

Specifications of AD7854

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 200kSPS
• Interface: Byte,Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (Vref) p-p
• Adc Architecture: SAR
• Pkg Type: DIP,SOIC,SOP

AD7854/AD7854L
CALIBRATION SECTION
Calibration Overview
The automatic calibration that is performed on power-up
ensures that the calibration options covered in this section are
not required in a significant number of applications. A calibration
does not have to be initiated unless the operating conditions
change (CLKIN frequency, analog input mode, reference volt-
age, temperature, and supply voltages). The AD7854/AD7854L
has a number of calibration features that may be required in
some applications, and there are a number of advantages in per-
forming these different types of calibration. First, the internal
errors in the ADC can be reduced significantly to give superior
dc performance; and second, system offset and gain errors can
be removed. This allows the user to remove reference errors
(whether it be internal or external reference) and to make use of
the full dynamic range of the AD7854/AD7854L by adjusting
the analog input range of the part for a specific system.
There are two main calibration modes on the AD7854/AD7854L,
self-calibration and system calibration. There are various op-
tions in both self-calibration and system calibration as outlined
previously in Table III. All the calibration functions are initi-
ated by writing to the control register and setting the STCAL
bit to 1.
The duration of each of the different types of calibration is given
in Table IX for the AD7854 with a 4 MHz master clock. These
calibration times are master clock dependent. Therefore the
calibration times for the AD7854L (CLKIN = 1.8 MHz) are
larger than those quoted in Table VIII.
Type of Self-Calibration or System Calibration
Automatic Calibration on Power-On
The automatic calibration on power-on is initiated by the first
CONVST pulse after the AV
CONVST pulse the part internally sets a 32/72 ms (4 MHz/
1.8 MHz CLKIN) timeout. This time is large enough to ensure
that the internal reference has settled before the calibration is
performed. However, if an external reference is being used, this
reference must have stabilized before the automatic calibration
is initiated. This first CONVST pulse also triggers the BUSY
signal high, and once the 32/72 ms has elapsed, the BUSY signal
goes low. At this point the next CONVST pulse that is applied
initiates the automatic full self-calibration. This CONVST pulse
again triggers the BUSY signal high, and after 32/72 ms (4 MHz/
1.8 MHz CLKIN), the calibration is completed and the BUSY
signal goes low. This timing arrangement is shown in Figure 28.
The times in Figure 28 assume a 4 MHz/1.8 MHz CLKIN
signal.
Table VIII. Calibration Times (AD7854 with 4 MHz CLKIN)
Full
Gain + Offset
Offset
Gain
DD
and DV
DD
power on. From the
Time
31.25 ms
6.94 ms
3.47 ms
3.47 ms
–20–
The CONVST signal is gated with the BUSY internally so that
as soon as the timeout is initiated by the first CONVST pulse all
subsequent CONVST pulses are ignored until the BUSY signal
goes low, 32/72 ms later. The CONVST pulse that follows after
the BUSY signal goes low initiates an automatic full self-
calibration. This takes a further 32/72 ms. After calibration,
the part is accurate to the 12-bit level and the specifications
quoted on the data sheet apply, and all subsequent CONVST
pulses initiate conversions. There is no need to perform another
calibration unless the operating conditions change or unless a
system calibration is required.
This autocalibration at power-on is disabled if the user writes to
the control register before the autocalibration is initiated. If the
control register write operation occurs during the first 32/72 ms
timeout period, then the BUSY signal stays high for the 32/72 ms
and the CONVST pulse that follows the BUSY going low does
not initiate an automatic full self-calibration. It initiates a con-
version and all subsequent CONVST pulses initiate conversions
as well. If the control register write operation occurs when the
automatic full self-calibration is in progress, then the calibration
is not be aborted; the BUSY signal remains high until the auto-
matic full self-calibration is complete.
Self-Calibration Description
There are four different calibration options within the self-
calibration mode. There is a full self-calibration where the
DAC, internal offset, and internal gain errors are removed.
There is the (Gain + Offset) self-calibration which removes the
internal gain error and then the internal offset errors. The inter-
nal DAC is not calibrated here. Finally, there are the self-offset
and self-gain calibrations which remove the internal offset errors
and the internal gain errors respectively.
The internal capacitor DAC is calibrated by trimming each of
the capacitors in the DAC. It is the ratio of these capacitors to
each other that is critical, and so the calibration algorithm
ensures that this ratio is at a specific value by the end of the
calibration routine. For the offset and gain there are two
separate capacitors, one of which is trimmed during offset
calibration and one of which is trimmed during gain calibration.
In bipolar mode the midscale error is adjusted by an offset cali-
bration and the positive full-scale error is adjusted by the gain
calibration. In unipolar mode the zero-scale error is adjusted by
the offset calibration and the positive full-scale error is adjusted
by the gain calibration.
AV
Figure 28. Timing Arrangement for Autocalibration on
Power-On
DD
CONVST
= DV
BUSY
DD
POWER ON
TIMEOUT PERIOD
32/72 ms
CALIBRATION
AUTOMATIC
DURATION
32/72 ms
CONVERSION IS INITIATED
ON THIS EDGE
REV. B