AD9223 Analog Devices, AD9223 Datasheet
AD9223
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AD9223 Summary of contents
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... Spurious-Free Dynamic Range Out-of-Range Indicator Straight Binary Output Data 28-Lead SOIC and 28-Lead SSOP GENERAL DESCRIPTION The AD9221, AD9223, and AD9220 are a generation of high performance, single supply 12-bit analog-to-digital converters. Each device exhibits true 12-bit linearity and temperature drift 1 performance as well as 11 ...
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... IDVDD POWER CONSUMPTION NOTES REF 2 Including internal reference. 3 Excluding internal reference. 4 Load regulation with 1 mA load current (in addition to that required by the AD9221/AD9223/AD9220). Specification subject to change without notice. = Max Conversion Rate 2.5 V, VINB = 2 SAMPLE REF AD9221 AD9223 AD9220 ...
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... Symbol OUT –3– AD9221/AD9223/AD9220 = 1.0 V, VINB = 2 Coupled/Single- REF AD9220 Unit 10.0 MHz min 1000 kHz 70 dB typ 68.5 dB min 11.3 dB typ 11.1 dB min 70.2 dB typ 69.0 dB min –83.7 dB typ –76.0 dB max 88.0 dB typ 77.5 dB max 5.0 MHz 67 ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9221/AD9223/AD9220 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Spurious Free Dynamic Range (SFDR) SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal. –5– AD9221/AD9223/AD9220 . ( ) = N SINAD – ...
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... AD9221/AD9223/AD9220 AD9221–Typical Performance Characteristics 1.0 0.8 0.6 0.4 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 0 4095 CODE TPC 1. Typical DNL 80 75 –0.5dB 70 –6.0dB –20.0dB 0.1 1.0 FREQUENCY – MHz TPC 4. SINAD vs. Input Frequency (Input Span = 2 –50 –55 –20.0dB –60 –65 – ...
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... AD9223–Typical Performance Characteristics 1.0 0.8 0.6 0.4 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 0 4095 CODE TPC 10. Typical DNL 80 75 –0.5dB 70 –6.0dB –20.0dB 0.1 1.0 10.0 FREQUENCY – MHz TPC 13. SINAD vs. Input Frequency (Input Span = 2 –50 –55 –60 –65 –20.0dB –70 – ...
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... AD9221/AD9223/AD9220 AD9220–Typical Performance Characteristics 1.0 0.8 0.6 0.4 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 1 4095 CODE TPC 19. Typical DNL 80 75 –0.5dB 70 –6dB –20dB 0.1 1.0 10.0 FREQUENCY – MHz TPC 22. SINAD vs. Input Frequency (Input Span = 2 –50 –55 –60 –20.0dB –65 –0.5dB – ...
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... The output drivers can be configured to interface with 3.3 V logic families. The AD9221/AD9223/AD9220 use both edges of the clock in their internal timing circuitry (see Figure 1 and Specifications for exact timing requirements). The A/D samples the analog input on the rising edge of the clock input ...
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... V input span) and matched S input impedance for VINA and VINB. Note that only a slight Q S2 degradation in dc linearity performance exists between the 2 V and 5 V input span as specified in the AD9221/AD9223 AD9220 DC Specifications. –10– , being CMOS switches ...
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... C the resulting R-C time constant is signal dependent and conse- quently a source of distortion. The noise or small-signal bandwidth of the AD9221/AD9223/ AD9220 is the same as their full-power bandwidth as shown in Figure 2. For noise sensitive applications, the excessive bandwidth may be detrimental and the addition of a series resistor and/or – ...
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... H Figure 9. Equivalent Reference Circuit The actual reference voltages used by the internal circuitry of the AD9221/AD9223/AD9220 appear on the CAPT and CAPB pins. For proper operation when using the internal or an external reference necessary to add a capacitor network to decouple these pins. Figure 10 shows the recommended decoupling net- work ...
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... VREF/2 2.5 – VREF/2 1.75 to 3.25 3.25 to 1.75 19 –13– AD9221/AD9223/AD9220 Comments Best for stepped input response applica- tions, suboptimum THD, and noise performance. Requires ± amp. Same as above but with improved noise performance due to increase in dynamic range. Headroom/settling time require- ments of ± amp should be evaluated. ...
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... Direct IF to Digital Conversion). Single-ended operation requires that VINA be ac- or dc-coupled to the input signal source while VINB of the AD9221/AD9223/ AD9220 can be biased to the appropriate voltage corresponding to a midscale code transition. Note that signal inversion may be easily accomplished by transposing VINA and VINB ...
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... If the application requires the largest input span (i.e the AD9221/AD9223/AD9220, the op amp will require larger supplies to drive it. Various high speed amplifiers in the Op Amp Selection Guide of this data sheet can be selected to accommodate a wide range of supply options ...
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... Since the common-mode voltage of VINA and VINB are biased to midsupply independent of VREF, VREF can be pin-strapped or reconfigured to achieve input spans between 2 V and 5 V p-p. The AD9221/AD9223/ AD9220’s CMRR along with the symmetrical coupling R-C networks will reject both power supply variations and noise. The resistors, R, establish the common-mode voltage. They may have a high value (e.g., 5 kΩ ...
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... In systems that do not need to be dc-coupled transformer with a center tap is the best method to generate differential inputs for the AD9221/ AD9223/AD9220. It provides all the benefits of operating the A/D in the differential mode without contributing additional noise or distortion transformer also has the added ben- efit of providing electrical isolation between the signal source and the A/D ...
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... VSWR. The center tap of the transformer provides a convenient means of level shifting the input signal to a desired common-mode voltage. Optimum performance can be realized when the center tap is tied to CML of the AD9221/AD9223/AD9220, which is the common-mode bias level of the internal SHA ...
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... Figure 19. In this case, the common-mode voltage set at midsupply by connecting the transformer’s center CM tap to CML of the AD9221/AD9223/AD9220. VREF can be configured for 2 connecting SENSE to either VREF or REFCOM respectively. Note that the valid input range for each of the differential inputs is one-half of single-ended input and thus becomes V – ...
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... REF-191, a 2.048 external reference was selected, the valid input range extends from 0 to 4.096 V. In this case, 1 LSB of the AD9221/AD9223/AD9220 corresponds essen- tial that a minimum µF capacitor in parallel with a 0.1 µF low inductance ceramic capacitor decouple the reference output to ground ...
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... Digital Output Driver Considerations (DVDD) The AD9221, AD9223 and AD9220 output drivers can be configured to interface with 3.3 V logic families by setting DVDD 3.3 V respectively. The AD9221/AD9223/ AD9220 output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause glitches on the supplies and may affect SINAD performance ...
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... The size and duration of these currents are a function of the load on the output bits: large capacitive loads are to be avoided. Note, the internal correction logic of the AD9221, AD9223, and AD9220 is referenced to AVDD while the output drivers are referenced to DVDD. ...
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... DAC08s, U3 and U5. The gain calibration circuitry consisting of U3, and an op amp, U2A, is configured to provide a low drift nominal 1.25 V reference to the AD9221/ AD9223/AD9220. The resistor values that set the gain calibra- 5 tion range were selected to provide a nominal adjustment span of ±128 LSBs with 1 LSB resolution with respect to the A/D. Note that the bandwidth of the reference is low and result not possible to change the reference voltage rapidly in this mode ...
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... The offset calibration circuitry consists of a DAC, U5 and the buffer amplifier, U4. The DAC is configured for a bipolar adjustment span of ± 64 LSB with a 1/2 LSB resolution span with respect to the AD9221/AD9223/AD9220. Note that both current outputs of U5 were configured to provide a bipolar adjustment span. Also used to decouple the output of both DACs, U3 and U5, from their respective op amps ...
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... EE A TPH DIG 6 TPI J5 JP4 DGND TPJ A VINA GJ1 J6 JP3 AGND (GJ1-WIRE A JUMPER CKT SIDE) Figure 36. Evaluation Board Schematic –25– AD9221/AD9223/AD9220 JP19 JP20 MSB 74HC541N 1 G1 Y0A Y5A Y1A BIT Y2A BIT ...
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... AD9221/AD9223/AD9220 Figure 37. Evaluation Board Component Side Layout (Not to Scale) Figure 38. Evaluation Board Solder Side Layout (Not to Scale) –26– REV. E ...
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... Figure 39. Evaluation Board Ground Plane Layout (Not to Scale) REV. E Figure 40. Evaluation Board Power Plane Layout –27– AD9221/AD9223/AD9220 ...
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... AD9221/AD9223/AD9220 Figure 41. Evaluation Board Component Side Silkscreen (Not to Scale) Figure 42. Evaluation Board Component Side Silkscreen (Not to Scale) –28– REV. E ...
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... PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters 10.50 10.20 9. 5.60 8.20 5.30 7.80 5.00 7. 1.85 1.75 0.10 1.65 COPLANARITY 0.25 0.09 0.38 0.65 BSC 0.22 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-150AH –29– AD9221/AD9223/AD9220 10.65 (0.4193) 10.00 (0.3937) 0.75 (0.0295) 45 0.25 (0.0098 1.27 (0.0500) 0.40 (0.0157) 8 0.95 4 0.75 0 0.55 ...
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... AD9221/AD9223/AD9220 Revision History Location 2/03—Data Sheet changed from REV REV. E. Updated graphic captions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Changes to DC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Changes to Digital Output Driver Considerations (DVDD) section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 –30– Page REV. E ...
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