AD5757 Analog Devices, AD5757 Datasheet
AD5757
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AD5757 Summary of contents
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... Actuator control PLCs HART network connectivity GENERAL DESCRIPTION The AD5757 is a quad, current output DAC that operates with a power supply range from 10 On-chip dynamic power control minimizes package power dissipation by regulat- ing the voltage on the output driver from 7 29.5 V using ...
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... Pin Configuration and Function Descriptions........................... 11 Typical Performance Characteristics ........................................... 14 Current Outputs ......................................................................... 14 DC-to-DC Block......................................................................... 19 Reference ..................................................................................... 20 General......................................................................................... 21 Terminology .................................................................................... 22 Theory of Operation ...................................................................... 23 DAC Architecture....................................................................... 23 Power-On State of the AD5757 ................................................ 23 Serial Interface ............................................................................ 23 Transfer Function ....................................................................... 24 Registers ........................................................................................... 25 Programming Sequence to Write/Enable the Output Correctly ...................................................................................... 26 Changing and Reprogramming the Range ............................. 26 Data Registers ............................................................................. 27 ...
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... Changes to Figure 4...........................................................................8 Changes to Figure 5...........................................................................9 Change to Pin 8 Description, Table 5 ...........................................11 Change to Figure 13 ........................................................................14 Change to Figure 20 ........................................................................16 Changes to Figure 48 and Power-On State of the AD5757 Section ..............................................................................................23 Change to Table 16..........................................................................29 Changes to Readback Operation Section, Readback Example Section, and Table 25 ......................................................................32 Change to Figure 54 ........................................................................35 Change to Figure 58 Caption ...
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... CONTROL SYNC SDO GAIN REG A FAULT OFFSET REG A STATUS REGISTER WATCHDOG ALERT TIMER (SPI ACTIVITY) REFOUT VREF DAC CHANNEL A REFERENCE REFIN BUFFERS DAC CHANNEL B AD1 AD5757 DAC CHANNEL C DAC CHANNEL D AD0 SW 7.4V TO 29.5V POWER CONTROL 16 DAC + DAC A REG Figure 2. ...
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... FSR 1000 Ω 100 MΩ 0.02 1 μA/V 5 5.05 V 150 MΩ Rev Page AD5757 = Test Conditions/Comments Assumes ideal resistor; see the External Current Setting Resistor section for more information Drift after 1000 hours 150°C J Guaranteed monotonic External R SET T = 25°C ...
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... AD5757 1 Parameter Min Reference Output Output Voltage 4.995 2 Reference TC −10 2 Output Noise (0 Hz) 2 Noise Spectral Density 2 Output Voltage Drift vs. Time 2 Capacitive Load Load Current Short-Circuit Current 2 Line Regulation 2 Load Regulation 2 Thermal Hysteresis DC-TO-DC Switch Switch On Resistance Switch Leakage Current Peak Current Limit ...
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... Rev Page Unit Test Conditions/Comments μs To 0.1% FSR ( mA) ms See Figure 26, Figure 27, and Figure 28 LSB p-p 16-bit LSB range nA/√Hz Measured at 10 kHz, midscale output range Figure 54 ) AD5757 = ...
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... AD5757 Timing Diagrams SCLK SYNC t 7 SDIN MSB LDAC I OUT_x LDAC = 0 I OUT_x CLEAR I OUT_x RESET SCLK 1 SYNC MSB SDIN INPUT WORD SPECIFIES REGISTER TO BE READ SDO UNDEFINED LSB ...
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... SDO DISABLED X X D15 D14 SDO_ STATUS STATUS ENAB Figure 5. Status Readback During Write 200µ (MIN OUTPUT OH PIN V (MAX 50pF 200µ Figure 6. Load Circuit for SDO Timing Diagram Rev Page AD5757 MSB STATUS STATUS ...
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... AD5757 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Transient currents 100 mA do not cause SCR latch-up. Table 4. Parameter Rating AGND, DGND −0 + BOOST_x AV to AGND −0 DGND −0 Digital Inputs to DGND − ...
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... TOP VIEW SDIN 9 (Not to Scale) SDO LDAC Figure 7. Pin Configuration Figure 3 ). Using this mode, all analog outputs can be updated simultaneously. The Rev Page AD5757 48 COMP DCDC_C 47 I OUT_C 46 V BOOST_C GNDSW C 42 GNDSW ...
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... AD5757 Pin No. Mnemonic Description 15 ALERT Active High Output. This pin is asserted when there has been no SPI activity on the interface pins for a predetermined time. See the Device Features section for more information. 16 FAULT Active Low Output. This pin is asserted low when an open circuit in current mode is detected, a short circuit in voltage mode is detected, a PEC error is detected overtemperature is detected (see the Device Features section) ...
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... Exposed Pad. This exposed pad should be connected to AGND, or, alternatively, it can be left electrically unconnected recommended that the pad be thermally connected to a copper plane for enhanced thermal performance. Supply Requirements—Slewing sections in the Device Features section for more CC Rev Page AD5757 OUT_D OUT_C ...
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... AD5757 TYPICAL PERFORMANCE CHARACTERISTICS CURRENT OUTPUTS 0.0025 AV = 15V DD 0.0020 T = 25°C A 0.0015 0.0010 0.0005 0 –0.0005 –0.0010 4mA TO 20mA, EXTERNAL R SET –0.0015 4mA TO 20mA, EXTERNAL R SET , WITH DC-TO-DC CONVERTER 4mA TO 20mA, INTERNAL R SET –0.0020 4mA TO 20mA, INTERNAL R SET , WITH DC-TO-DC CONVERTER 4mA TO 20mA, EXTERNAL R SET , EXTERNAL PMOS MODE – ...
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... Figure 18. Integral Nonlinearity Error vs. AV Over Supply, External R SET 0 4mA TO 20mA RANGE MAX INL 4mA TO 20mA RANGE MIN INL T = 25° SUPPLY (V) Figure 19. Integral Nonlinearity Error vs. AV Over Supply, Internal R SET AD5757 SET SET SET SET SET SET 80 100 ...
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... AD5757 1.0 ALL RANGES INTERNAL AND EXTERNAL R 0.8 SET T = 25°C A 0.6 0.4 0.2 DNL ERROR MAX 0 DNL ERROR MIN –0.2 –0.4 –0.6 –0.8 –1 SUPPLY (V) Figure 20. Differential Nonlinearity Error vs. AV 0.012 0.010 0.008 0.006 0.004 4mA TO 20mA RANGE MAX TUE 4mA TO 20mA RANGE MIN TUE ...
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... INDUCTOR = 10µH (XAL4040-103 25° –0.25 0 0.25 0.50 0.75 1.00 1.25 TIME (ms) AV (See Figure 56 (4mA TO 20mA STEP) OUT 25°C A EXTERNAL PMOS (NTLJS4149) 4mA TO 20mA RANGE R = 300Ω LOAD V = 24V 10 BOOST_X I (20mA TO 4mA STEP) OUT 5 0 – TIME (µs) AD5757 1.50 1. ...
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... AD5757 10 20mA OUTPUT 10mA OUTPUT –2 –4 –6 – 410kHz SW INDUCTOR = 10µH (XAL4040-103) – TIME (µs) Figure 30. Output Current vs. Time with DC-to-DC Converter (See Figure 56) 8 0mA TO 24mA RANGE 1kΩ LOAD 410kHz SW INDUCTOR = 10µH (XAL4040-103) ...
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... TO 24mA RANGE 1kΩ LOAD EXTERNAL R SET 410 kHz SW INDUCTOR = 10µH (XAL4040-103) 20 –40 – TEMPERATURE (°C) Figure 36. Output Efficiency vs. Temperature (See Figure 56) 0.6 0.5 0.4 0.3 0.2 0.1 0 –40 – TEMPERATURE (°C) Figure 37. Switch Resistance vs. Temperature AD5757 80 100 80 100 ...
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... Figure 41. REFOUT vs. Temperature (When the AD5757 is soldered onto a PCB, the reference shifts due to thermal shock on the package. The average output voltage shift is –4 mV. Measurement of these parts after seven days shows that the outputs typically shift back 2 mV toward their initial values. ...
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... 25° 25° 0mA OUT Rev Page 13.4 13.3 13.2 13.1 13.0 12.9 12.8 12 5.5V CC 12.6 –40 – TEMPERATURE (°C) Figure 46. Internal Oscillator Frequency vs. Temperature 14.4 14.2 14.0 13.8 13.6 13 25°C A 13.0 2.5 3.0 3.5 4.0 4.5 VOLTAGE (V) Figure 47. Internal Oscillator Frequency vs AD5757 80 100 5.0 5.5 Supply Voltage ...
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... Power-On Glitch Energy Power-on glitch energy is the impulse injected into the analog output when the AD5757 is powered-on specified as the area of the glitch in nV-sec. See Figure 24. Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the power supply voltage ...
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... SERIAL INTERFACE The AD5757 is controlled over a versatile 3-wire serial interface that operates at clock rates MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP standards. Data coding is always straight binary ...
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... AD5757 TRANSFER FUNCTION For the mA mA, and current output ranges, the output current is respectively expressed as ⎡ ⎤ × I ⎢ ⎥ D OUT N ⎣ ⎦ 2 ⎡ ⎤ × ⎢ ⎥ OUT N ⎣ ⎦ 2 ⎡ ...
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... Used to program offset trim per channel basis. AD5757 data bits = D15 to D0. There are four offset registers, one per DAC channel. Clear Code Register (×4) Used to program clear code on a per channel basis. AD5757 data bits = D15 to D0. There are four clear code registers, one per DAC channel. Control Main Control Register Used to configure the part for main operation ...
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... AD5757 PROGRAMMING SEQUENCE TO WRITE/ENABLE THE OUTPUT CORRECTLY To correctly write to and set up the part from a power-on condition, use the following sequence: 1. Perform a hardware or software reset after initial power-on. 2. The dc-to-dc converter supply block must be configured. Set the dc-to-dc switching frequency, maximum output voltage allowed, and the phase that the four dc-to-dc channels clock at ...
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... DUT_AD0 Table 8. Input Register Decode Bit Description R/W Indicates a read from or a write to the addressed register. DUT_AD1, DUT_AD0 Used in association with the external pins, AD1 and AD0, to determine which AD5757 device is being addressed by the system controller. DUT_AD1 DREG2, DREG1, DREG0 Selects whether a data register or a control register is written to ...
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... AD5757 Gain Register The 16-bit gain register, as shown in Table 10, allows the user to adjust the gain of each channel in steps of 1 LSB. This is done by setting the DREG[2:0] bits to 010 possible to write the same gain code to all four DAC channels at the same time by setting the DREG[2:0] bits to 011 ...
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... DAC control register (one per channel) 1 DC-to-dc control register 0 Software register D10 EWD WD1 WD0 X X Timeout Period (ms 100 200 Rev Page AD5757 LSB D15 D14 D13 D12 to D0 CREG2 CREG1 CREG0 Data OUTEN_ALL DCDC_ALL X LSB ...
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... AD5757 DAC Control Register The DAC control register is used to configure each DAC channel. The DAC control register options are shown in Table 19 and Table 20. Table 19. Programming DAC Control Register D15 D14 D13 D12 D11 D10 don’t care. ...
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... D11, in the status register also used as part of the watchdog feature when it is enabled. This feature is useful to ensure that communication has not been lost between the MCU and the AD5757 and that the datapath lines are working properly (that is, SDIN, SCLK, and SYNC ). Table 21. Programming the Software Register ...
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... To read back the gain register of Device 1, Channel A on the AD5757, implement the following sequence: 1. Write 0xA80000 to the AD5757 input register. This configures the AD5757 Device Address 1 for read mode with the gain register of Channel A selected. All the data bits, D15 to D0, are don’t cares. 2. ...
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... Ramp Active This bit is set while any one of the output channels is slewing (slew rate control is enabled on at least one channel). Over TEMP This bit is set if the AD5757 core temperature exceeds approximately 150°C. I Fault This bit is set if a fault is detected on the I ...
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... This is added to the end of the data-word, and 32 bits are sent to the AD5757 before taking SYNC high. If the AD5757 sees a 32-bit frame, it performs the error check when SYNC goes high. If the check is valid, the data is written to the selected register. Rev Page ...
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... Table 17 and Table 18). OUTPUT ALERT The AD5757 is equipped with an ALERT pin. This is an active high CMOS output. The AD5757 also has an internal watchdog timer. When enabled, it monitors SPI communications. If 0x195 is not received by the software register within the timeout period, the ALERT pin goes active ...
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... HART. DIGITAL SLEW RATE CONTROL The slew rate control feature of the AD5757 allows the user to control the rate at which the output value changes. With the slew rate control feature disabled, the output value changes at a rate limited by the output drive circuitry and the attached load ...
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... DC-to-DC Converter Operation The on-board dc-to-dc converters use a constant frequency, peak current mode control scheme to step 4 5 drive the AD5757 output channel. These are designed to operate in discontinuous conduction mode (DCM) with a duty cycle of <90% typical. Discontinuous conduction mode refers to a mode of operation where the inductor current goes to zero for an appreciable percentage of the switching cycle. The dc-to-dc converters are nonsynchronous ...
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... The input capacitor provides much of the dynamic current required for the dc-to-dc converter and should be a low ESR component. For the AD5757, a low ESR tantalum or ceramic capacitor of 10 μF is recommended for typical applications. Ceramic capacitors must be chosen carefully because they can exhibit a large sensitivity to dc bias voltages and temperature ...
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... Figure 61 EXTERNAL PMOS MODE 28 The AD5757 can also be used with an external PMOS transistor 500Ω LOAD f = 410kHz per channel, as shown in Figure 62. This mode can be used 25°C limit the on-chip power dissipation of the AD5757, though this A 20 will not reduce the power dissipation of the total system ...
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... I a load of 50 mH. The capacitive component of the load may cause slower settling, although this may be masked by the set- tling time of the AD5757. There is no maximum capacitance limit for the current output of the AD5757. Temperature Drift (ppm/°C Maximum) ...
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... Traces The power supply lines of the AD5757 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to prevent radiating noise to other parts of the board and should never be run near the reference inputs ...
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... Analog Devices i Coupler® products can provide voltage isolation in , close excess of 2.5 kV. The serial loading structure of the AD5757 makes it ideal for isolated interfaces because the number of through the inductor, IN interface lines is kept to a minimum. Figure 65 shows a 4-channel isolated interface to the AD5757 using an ADuM1400 ...
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... Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Rev Page 0.60 MAX PIN 1 INDICATOR 64 1 7.25 EXPOSED PAD 7.10 SQ (BOTTOM VIEW) 6. 0.25 MIN 7.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. AD5757 Package Option CP-64-3 CP-64-3 ...
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... AD5757 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09225-0-11/11(B) Rev Page Data Sheet ...