AD9739A Analog Devices, AD9739A Datasheet
AD9739A
Specifications of AD9739A
Available stocks
Related parts for AD9739A
AD9739A Summary of contents
Page 1
... Trademarks and registered trademarks are the property of their respective owners. RF Digital-to-Analog Converters SDIO SDO CS SCLK DCI DCO The AD9737A/AD9739A CMOS process and operate from 1.8 V and 3.3 V supplies. They are supplied in a 160-ball chip scale ball grid array for are pin with the reduced package parasitics. do not support PRODUCT HIGHLIGHTS 1. ...
Page 2
... Interrupt Requests ...................................................................... 54 Analog Interface Considerations .................................................. 55 Analog Modes of Operation ..................................................... 55 Clock Input Considerations ...................................................... 56 Voltage Reference ....................................................................... 57 Analog Outputs .......................................................................... 57 Output Stage Configuration ..................................................... 59 Nonideal Spectral Artifacts ....................................................... 60 Lab Evaluation of the AD9737A/AD9739A ........................... 61 Recommended Start-Up Sequence .......................................... 61 Outline Dimensions ....................................................................... 63 Ordering Guide .......................................................................... 63 C Rev. | Page Data Sheet ) and Sleep ........... 44 OUTFS ...
Page 3
... Rev. A Changed Maximum Update Rate (DACCLK Input) Parameter to DAC Clock Rate Parameter in Table 4 ....................................... 6 Added Adjusted DAC Update Rate Parameter and Endnote 1 in Table 4 ................................................................................................. 6 Updated Outline Dimensions ........................................................ 43 1/11—Revision 0: Initial Version Rev Page AD9737A/AD9739A ) and Sleep Section, TxDAC OUTFS ...
Page 4
... Typ 11 ±0.5 ±0.5 5.5 8.66 20.2 −1 1.2 1.6 900 1 1.15 1.2 5 3.1 3.3 1.70 1.8 3.10 3.3 1.70 1.8 37 158 14.5 173 0.770 2.5 0.02 6 0.6 0.1 223 14.5 215 0.960 C Rev. | Page Data Sheet AD9739A Max Min Typ Max Unit 14 Bits ±2.5 LSB ±2.0 LSB 5.5 % 31.66 8.66 20.2 31.66 mA +1.0 −1.0 +1 MΩ 70 Ω 2.0 1.2 1.6 2.0 V 900 mV 2.5 1.6 2.5 GHz 60 ppm/°C 20 ppm/°C 1.25 1 ...
Page 5
... DCO_P and DCO_N pins with 100 Ω differential termination mA. LVDS drivers and receivers are compliant to the IEEE Standard 1596.3- OUTFS 1 COM IH_DTH IL_DTH IN ) (See Figure 159) COM IH_DTH IL_DTH IN C Rev. | Page AD9737A/AD9739A Min Typ Max 825 1575 175 400 −175 −400 80 120 1.2 1250 344 ...
Page 6
... AD9737A/AD9739A SERIAL PORT SPECIFICATIONS VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V. Table 3 . Parameter WRITE OPERATION (See Figure 154) SCLK Clock Rate 1/t SCLK SCLK SCLK Clock High, t HIGH SCLK Clock Low, t LOW SDIO to SCLK Setup Time SCLK to SDIO Hold Time SCLK Setup Time, t ...
Page 7
... Typ 1600 1600 −162 −162 −161 −161 80/81 75/75 69/71 66/67 divided by the minimum required interpolation factor. For the AD9737A/AD9739A, the minimum interpolation factor C Rev. | Page AD9737A/AD9739A AD9739A Max Min Typ Max 2500 1600 2500 2500 1600 2500 ...
Page 8
... AD9737A/AD9739A ABSOLUTE MAXIMUM RATINGS Table 5. Parameter VDDA to VSSA VDD33 to VSS VDD to VSS VDDC to VSSC VSSA to VSS VSSA to VSSC VSS to VSSC DACCLK_P, DACCLK_N to VSSC DCI, DCO to VSS LVDS Data Inputs to VSS IOUTP, IOUTN to VSSA I120, VREF to VSSA IRQ, CS, SCLK, SDO, SDIO, RESET to VSS ...
Page 9
... F G AD9737A Figure 5. AD9737A Digital LVDS Input, Clock I/O (Top View AD9739A Figure 6. AD9739A Digital LVDS Input, Clock I/O (Top View DCO_P/_N DCI_P/_N 14 DCO_P/_N DCI_P/_N ...
Page 10
... AD9737A/AD9739A Table 7. AD9737A Pin Function Descriptions Pin No. C1, C2, D1, D2, E1, E2, E3, E4 A1, A2, A3, A4, A5, B1, B2, B3, B4, B5, C4, C5, D4, D5 A10, A11, B10, B11, C10, C11, D10, D11 A12, A13, B12, B13, C12, C13, D12, D13, ...
Page 11
... Port 0 Positive/Negative Data Input Bit 5. DB0[6]P/DB0[6]N Port 0 Positive/Negative Data Input Bit 6. DB0[7]P/DB0[7]N Port 0 Positive/Negative Data Input Bit 7. DB0[8]P/DB0[8]N Port 0 Positive/Negative Data Input Bit 8. DB0[9]P/DB0[9]N Port 0 Positive/Negative Data Input Bit 9. DB0[10]P/DB0[10]N Port 0 Positive/Negative Data Input Bit 10. Rev Page AD9737A/AD9739A ...
Page 12
... AD9739A Figure 8. AD9739A Analog I/O and SPI Control Pins (Top View) Mnemonic Description VDDC 1.8 V Clock Supply Input. VSSC Clock Supply Ground. VDDA 3.3 V Analog Supply Input. VSSA Analog Supply Ground. VSSA Shield Analog Supply Ground Shield. Tie to VSSA at the DAC. ...
Page 13
... Port 0 Positive/Negative Data Input Bit 8. DB0[9]P/DB0[9]N Port 0 Positive/Negative Data Input Bit 9. DB0[10]P/DB0[10]N Port 0 Positive/Negative Data Input Bit 10. DB0[11]P/DB0[11]N Port 0 Positive/Negative Data Input Bit 11. DB0[12]P/DB0[12]N Port 0 Positive/Negative Data Input Bit 12. DB0[13]P/DB0[13]N Port 0 Positive/Negative Data Input Bit 13. Rev Page AD9737A/AD9739A ...
Page 14
... AD9737A/AD9739A TYPICAL PERFORMANCE CHARACTERISTICS—AD9737A STATIC LINEARITY mA, nominal supplies 25°C, unless otherwise noted. OUTFS A 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 0 256 512 768 1024 1280 CODE Figure 9. Typical INL 25°C 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 0 256 512 768 1024 1280 CODE Figure 10. Typical DNL 25° ...
Page 15
... OUT Figure 17. SFDR vs. f over f OUT STOP 2.4GHz = 2.4 GSPS DAC STOP 2.4GHz = 2.4 GSPS DAC 2.4GSPS 800 1000 1200 DAC C Rev. | Page AD9737A/AD9739A 120 1.2GSPS 100 1.6GSPS 80 2.0GSPS 2.4GSPS 200 400 600 800 1000 f (MHz) OUT Figure 18 ...
Page 16
... AD9737A/AD9739A GSPS mA, nominal supplies, T DAC OUTFS 90 85 –6dBFS 80 75 –3dBFS 0dBFS 100 200 300 400 500 600 f (MHz) OUT Figure 21. SFDR vs. f over Digital Full Scale OUT 90 –6dBFS 80 –3dBFS 70 60 0dBFS 200 400 ...
Page 17
... Figure 29. Single-Tone NSD vs. f OUT = 25°C, unless otherwise noted. A 700 800 900 1000 700 800 900 1000 700 800 900 1000 over Temperature C Rev. | Page AD9737A/AD9739A –150 –152 –154 –156 –158 +85°C –160 –162 –164 +25°C –166 –168 –170 0 100 200 300 400 ...
Page 18
... AD9737A/AD9739A f = 2.1 GSPS mA, nominal supplies, T DAC OUTFS START 20MHz #RES BW 20kHz SWEEP 7.174s (601pts) VBW 20kHz Figure 33. Single-Tone Spectrum 2.31 GHz, f OUT START 20MHz #RES BW 20kHz SWEEP 7.174s (601pts) VBW 20kHz Figure 34. Single-Tone Spectrum 1.31 GHz, f OUT ...
Page 19
... SPAN 69.68MHz SWEEP 1.922s FILTER Rev. | Page AD9737A/AD9739A –58.0dBc –58.0dBc –37.4dBm –37.1dBm –58.2dBc –58.0dBc –57.9dBc –58.0dBc –37.1dBm –36.9dBm –58.1dBc –60 – ...
Page 20
... AD9737A/AD9739A ONE-CARRIER DOCSIS PERFORMANCE (NORMAL MODE mA 2.4576 GSPS, nominal supplies, T OUTFS DAC –30 1 –40 –50 –60 –70 –80 –90 5Δ1 –100 2Δ1 3Δ1 –110 START 50MHz VBW 2kHz #RES BW 20kHz SWEEP 24.1s (1001pts) MKR MODE TRC SCL X Y FUNCTION 200 ...
Page 21
... C Rev. | Page AD9737A/AD9739A –40 –17.9dBc –50 –53.2dBc 0dBc 0.1dBc –0.6dBc –73.3dBc –72.9dBc –60 –70 –80 –90 –100 – ...
Page 22
... AD9737A/AD9739A EIGHT-CARRIER DOCSIS PERFORMANCE (NORMAL MODE mA 2.4576 GSPS, nominal supplies, T OUTFS DAC –40 1 –50 –60 –70 –80 –90 3Δ1 –100 2Δ1 –110 –120 START 50MHz VBW 2kHz #RES BW 20kHz SWEEP 24.1s (1001pts) MKR MODE TRC SCL X Y FUNCTION 200.10MHz – ...
Page 23
... C Rev. | Page AD9737A/AD9739A 0.0dBc –0.1dBc –0.2dBc –0.3dBc –26.3dBm –65.2dBc –63.9dBc –50 –60 –70 –80 –90 –100 –110 – ...
Page 24
... AD9737A/AD9739A 32-CARRIER DOCSIS PERFORMANCE (NORMAL MODE mA 2.4576 GSPS, nominal supplies, T OUTFS DAC –50 1 –60 –70 –80 –90 –100 4Δ1 –110 3Δ1 2Δ1 –120 –130 START 50MHz VBW 2kHz #RES BW 20kHz SWEEP 24.1s (1001pts) MKR MODE TRC SCL X Y FUNCTION 256 ...
Page 25
... FUNCTION FUNCTION WIDTH VALUE 6MHz –35.909dBm (Δ) 6MHz –53.920dB 6MHz –38.646dBm C Rev. | Page AD9737A/AD9739A 0.1dBc 0.1dBc 0.0dBc –0.4dBc –33.4dBm –60.0dBc –58.7dBc –59.0dBc CENTER 448MHz SPAN 54MHz VBW 3kHz #RES BW 30kHz SWEEP 1.49s CARRIER POWER – ...
Page 26
... AD9737A/AD9739A TYPICAL PERFORMANCE CHARACTERISTICS—AD9739A STATIC LINEARITY 3.0 2.5 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE Figure 78. Typical INL 25°C 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE Figure 79. Typical DNL 25° ...
Page 27
... Figure 87. Typical DNL 25°C 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 250 500 750 Figure 88. Power Consumption vs Rev. | Page AD9737A/AD9739A 8192 10,240 12,288 14,336 16,384 CODE TOTAL DVDD18 CLKVDD AVDD DVDD33 1000 1250 1500 1750 2000 2250 2500 f (MHz) DAC at 25°C DAC ...
Page 28
... AD9737A/AD9739A AC (NORMAL MODE mA, nominal supplies 25°C, unless otherwise noted. OUTFS A START 20MHz VBW 10kHz Figure 89. Single-Tone Spectrum MHz, f OUT 80 1.2GSPS 1.6GSPS 2.4GSPS 55 2.0GSPS 100 200 300 400 500 600 700 800 900 1000 1100 1200 ...
Page 29
... Digital Full Scale Figure 99. SFDR for Third Harmonic over f 110 100 800 900 1000 OUTFS C Rev. | Page AD9737A/AD9739A –6dBFS –3dBFS 0 100 200 300 400 500 600 700 800 f (MHz) OUT Figure 98. IMD vs. f over Digital Full Scale OUT – ...
Page 30
... AD9737A/AD9739A GSPS mA, nominal supplies, T DAC OUTFS –40°C 60 +25° 100 200 300 400 500 600 f (MHz) OUT Figure 101. SFDR vs. f over Temperature OUT –150 –152 –154 –156 –158 –160 –162 +85°C –164 –166 +25°C – ...
Page 31
... SPAN 53.84MHz UPPER (dBc) (dBm) –90.37 –92.50 –92.77 –94.03 –94.70 Figure 112. Single-Carrier WCDMA ACLR vs Rev. | Page AD9737A/AD9739A START 20MHz START 20MHz #RES BW 10kHz SWEEP 28.7s (601pts) VBW 10kHz f = 2.4 GSPS DAC ...
Page 32
... AD9737A/AD9739A f = 2.4 GSPS mA, nominal supplies, T DAC OUTFS CENTER 2.807GHz #RES BW 30kHz SWEEP 174.6ms (601pts) VBW 300kHz FREQ REF RMS RESULTS OFFSET BW LOWER (MHz) (MHz) (dBc) (dBm) CARRIER POWER 5 3.84 –64.90 –89.30 –24.4dBm/ 10 3.84 –66.27 –90.67 3.84MHz 15 3.84 –68.44 –92.84 20 3.84 –70.20 –94.60 25 3.84 –70.85 –95.25 Figure 113 ...
Page 33
... C Rev. | Page AD9737A/AD9739A –80.7dBc –80.7dBc –80.7dBc –81.2dBc –10.2dBm –81.3Bc –80.7dBc –35 –45 –55 –65 –75 –85 –95 – ...
Page 34
... AD9737A/AD9739A FOUR-CARRIER DOCSIS PERFORMANCE (NORMAL MODE mA 2.4576 GSPS, nominal supplies, T OUTFS DAC 1 –40 –50 –60 –70 –80 –90 –100 –110 5Δ1 3Δ1 2Δ1 –120 START 50MHz VBW 2kHz #RES BW 20kHz SWEEP 24.1s (1001pts) MKR MODE TRC SCL X Y FUNCTION ...
Page 35
... C Rev. | Page AD9737A/AD9739A 0.0dBc 0.0dBc 0.1dBc –0.3dBc –21.9dBm –70.0Bc –69.9dBc –37 –47 –57 –67 –77 –87 –97 –107 – ...
Page 36
... AD9737A/AD9739A 16-CARRIER DOCSIS PERFORMANCE (NORMAL MODE mA 2.4576 GSPS, nominal supplies, T OUTFS DAC –38 1 –48 –58 –68 –78 –88 –98 –108 6Δ1 5Δ1 2Δ1 3Δ1 –118 START 50MHz VBW 2kHz #RES BW 20kHz SWEEP 24.1s (1001pts) MKR MODE TRC SCL X Y FUNCTION ...
Page 37
... WIDTH VALUE 6MHz –31.516dBm (Δ) 6MHz –59.997dB (Δ) 6MHz –60.535dB (Δ) 6MHz –57.763dB C Rev. | Page AD9737A/AD9739A 0.1dBc 0.0dBc –0.1dBc –0.4dBc –29.9dBm –65.4dBc –64.8dBc –44 –54 –64 –74 –84 –94 –104 –114 – ...
Page 38
... AD9737A/AD9739A 64- AND 128-CARRIER DOCSIS PERFORMANCE (NORMAL MODE mA 2.4576 GSPS, nominal supplies, T OUTFS DAC –52 1 –62 –72 –82 –92 –102 3Δ1 –112 –122 –132 START 50MHz VBW 2kHz #RES BW 20kHz SWEEP 24.1s (1001pts) MKR MODE TRC SCL X Y FUNCTION 478.75MHz – ...
Page 39
... For offset and gain Intermodulation Distortion (IMD) IMD is the result of two or more signals at different frequencies mixing together. Many products are created according to the formula, aF1 ± bF2, where a and b are integer values. C Rev. | Page AD9737A/AD9739A ...
Page 40
... CS can be raised after each sequence of eight bits (except the last byte) to stall the bus. The serial transfer resumes when CS is lowered. Stalling on nonbyte boundaries resets the SPI. C Rev. | Page Data Sheet AD9737A/AD9739A, shown in Figure 152, SDO (PIN H14) SDIO (PIN G14) AD9737A/AD9739A SPI PORT ...
Page 41
... R/W Figure 155. SPI 3-Wire Read Operation Timing SCLK t t LOW R Figure 156. SPI 4-Wire Read Operation Timing C Rev. | Page AD9737A/AD9739A ...
Page 42
... AD9737A/AD9739A SPI REGISTER MAP Table 10. Full Register Map (N/A = Not Applicable) Name Address Bit 7 Bit 6 Mode 0x00 SDIO_DIR LSB/MSB Power- 0x01 N/A N/A Down CNT_CLK_ 0x02 N/A N/A DIS IRQ_EN 0x03 N/A N/A IRQ_REQ 0x04 N/A N/A RSVD 0x05 N/A N/A FSC_1 0x06 FSC[7] FSC[6] FSC_2 0x07 Sleep N/A DEC_CNT 0x08 N/A N/A RSVD 0x09 ...
Page 43
... R/W 0x0 R/W 0x0 Default R/W Setting Description R/W 0x0 Internal CLK distribution enable enable disable. R/W 0x1 LVDS receiver and Mu controller clock disable disable enable. R/W 0x1 C Rev. | Page AD9737A/AD9739A Bit 2 Bit 1 Bit 0 CLKN_ CLKN_ CLKN_ OFFSET[2] OFFSET[1] OFFSET[0] N/A N/A N/A N/A N/A N/A Gain[1] Gain[0] Enable SET_PHS[2] SET_PHS[1] ...
Page 44
... AD9737A/AD9739A INTERRUPT REQUEST (IRQ) ENABLE/STATUS Table 14. Interrupt Request (IRQ) Enable (IRQ_EN)/Status (IRQ_REQ) Register Address (Hex) Bit Name Bits 0x03 MU_LST_EN 3 MU_LCK_EN 2 RCV_LST_EN 1 RCV_LCK_EN 0 0x04 MU_LST_IRQ 3 MU_LCK_IRQ 2 RCV_LST_IRQ 1 RCV_LCK_IRQ 0 TxDAC FULL-SCALE CURRENT SETTING (I Table 15. TxDAC Full-Scale Current Setting (I Address (Hex) Bit Name ...
Page 45
... Default R/W Setting Description R 0x0 0 = tracking not established tracking established. R 0x0 0 = find edge state machine is not active find edge state machine is active. R 0x0 0 = controller has not lost lock controller has lost lock. R 0x0 0 = controller is not locked controller is locked. C Rev. | Page AD9737A/AD9739A ...
Page 46
... AD9737A/AD9739A CLK INPUT COMMON MODE Table 23. CLK Input Common Mode Register (CROSS_CNT1 and CROSS_CNT2) Address (Hex) Bit Name Bits 0x22 DIR_P 4 CLKP_OFFSET[3:0] [3:0] 0x23 DIR_N 4 CLKN_OFFSET[3:0] [3:0] MU CONTROLLER CONFIGURATION AND STATUS Table 24. Mu Controller Configuration and Status Register (PHS_DET, MU_DUTY, MU_CNT[1:4], and MU_STAT1) ...
Page 47
... Decimal 11 or 0x0B). R 0x0 controller has not lost lock controller has lost lock. R 0x0 controller is not locked controller is locked. Default R/W Setting Description R 0x24 0x24—AD9739A 0x27 0x27—AD9737A C Rev. | Page AD9737A/AD9739A ...
Page 48
... AD9737A are 14- and 11-bit TxDACs with a specified update rate of 1.6 GSPS to 2.5 GSPS. Figure 157 shows a top-level functional diagram of the AD9737A/AD9739A. A high performance TxDAC core delivers a signal dependent, differential current (nominal ±10 mA balanced load referenced to ground. The frequency of the clock signal appearing ...
Page 49
... DAC VALID GUARD t VALID Figure 159. LVDS Data Port Timing Requirements C Rev. | Page AD9737A/AD9739A = 800 ps − 344 ps − 100 ps = 356 ps and Guard is VALID in Figure 159. GUARD AD9737A/AD9739A /4) to maintain the lowest skew variation between DAC AD9737A/AD9739A internal digital max skew ...
Page 50
... Bit 1 and Bit 0). Tracking mode operates cont- inuously in the background to track delay variations between the host and AD9737A/AD9739A clock domains. It does so by ensuring that the DCI signal is sampled within a very narrow window defined by two internally generated clocks (that is, PRE and PST), as shown in Figure 161 ...
Page 51
... On initialization of the AD9737A/AD9739A, a certain period of time is required for the data receiver controller to establish a lock of the DCI clock signal. Note that, due to its dependency on the ...
Page 52
... The target Mu phase (and slope) is selected to provide optimum ac performance while ensuring that the Mu controller AD9737A/AD9739A for any device can establish and maintain lock. For example, although a slope and phase setting of −6 is considered optimum for operation between 1 ...
Page 53
... Bit 0) after the typical locking time has expired. This method lets the system controller check the status of other system parameters (that is, power supplies and clock source) before reattempting the search (by writing 0x03 to Register 0x26). C Rev. | Page AD9737A/AD9739A data sheet specifications and characterization ...
Page 54
... C Rev. | Page Data Sheet (PIN F13) INT INT(n) SOURCE Q SPI ISR READ DATA SPI WRITE SPI ADDRESS DATA = 1 AD9737A/AD9739A Description MU_LST_EN MU_LCK_EN RCV_LST_EN RCV_LCK_EN MU_LST_IRQ MU_LCK_IRQ RCV_LST_IRQ RCV_LCK_IRQ RCVR_TRK_ON RCVR_LST RCVR_LCK MU_LST MU_LKD ...
Page 55
... –10 – –20 – –30 –35 C Rev. | Page AD9737A/AD9739A INPUT DATA DACCLK_x D – – – MIX MODE) D – ...
Page 56
... Each single-ended output can provide a squared-up output level that can be varied from −4 dBm to +5 dBm, allowing for >2 V p-p output differential swings. The an additional CML buffer that can be used to drive another /f ) AD9737A/AD9739A OUT CLK AD9737A/AD9739A ADCLK914 driven Rev. | Page AD9737A/AD9739A 50Ω 50Ω 10nF ...
Page 57
... However, because the ac signal-dependent current component is complementary, the sum of the two outputs is always constant (that is, IOUTP + IOUTN = (34/32) × OUTFS C Rev. | Page AD9737A/AD9739A to the FSC[9:0] bits, which OUTFS = 22.6 × FSC[9:0]/1000 + 8.7 provide complementary current AD9737A/AD9739A outputs exhibit a /16), and the peak differential OUTFS /2 (that is, 15/32 × ...
Page 58
... R SOURCE = 50Ω 8.6 – 31.2mA OUTFS = AC 180Ω 70Ω Figure 180. Equivalent Circuit for Determining Maximum Peak Power Ω Load C Rev. | Page AD9737A/AD9739A are programmed for I 2 R). Because the source OUTFS LOSSLESS R BALUN LOAD = 50Ω 1:1 Data Sheet = 20 mA, OUTFS , although any ...
Page 59
... Any imbalance in the output impedance between the IOUTP and IOUTN pins results in asymmetrical signal swings that degrade the distortion performance (mostly even order) and noise performance. Component selection and layout are critical in realizing the performance potential of the AD9737A/AD9739A. IOUTP 90Ω 70Ω ...
Page 60
... C Rev. | Page Images appear as replicas of the original signal, hence, can be easier to identify. In the case of the AD9737A/AD9739A, internal modulation of the sampling clock at intervals related generate image pairs at ¼ × f DAC and ¾ × Both upper and lower sideband images DAC associated with ¼ ...
Page 61
... REOUT Figure 187. Lab Test Setup Used to Characterize the RECOMMENDED START-UP SEQUENCE On power-up of the AD9737A/AD9739A, a host processor is required to initialize and configure the via its SPI port. Figure 188 shows a flowchart of the sequential steps required. Table 29 provides more detail on the SPI register ...
Page 62
... not locked, return to Step 10 and repeat. Limit attempts to three before breaking out of the loop and reporting a Mu lock failure. Ensure that the AD9737A/AD9739A are fed with DCI clock input from the data source. Set FINE_DEL_SKEW to 2. Disable the data Rx controller before enabling it. ...
Page 63
... Chip Scale Package Ball Grid Array [CSP_BGA] 160- Ball Chip Scale Package Ball Grid Array [CSP_BGA] Evaluation Board for Normal, CMTS, and Mix-Mode Evaluation Evaluation Board with FMC connector for Xilinx based FPGA development platforms Rev Page AD9737A/AD9739A A1 BALL CORNER ...
Page 64
... AD9737A/AD9739A NOTES ©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09616-0-2/12(C) Rev Page Data Sheet ...