CS44600-CQZ Cirrus Logic Inc, CS44600-CQZ Datasheet
CS44600-CQZ
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CS44600-CQZ Summary of contents
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... Limiter Modulator Multibit Volume Σ∆ / Limiter Modulator SRC Multibit Volume Σ∆ / Limiter Modulator Copyright © Cirrus Logic, Inc. 2006 (All Rights Reserved) CS44600 ® Host Control Interfaces PSR_RESET Power PSR_EN Supply PSR_MCLK PSR_SYNC Rejection PSR_DATA PWMOUTA1+ PWM PWMOUTA1- Conversion ...
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... This efficiency provides for smaller device package, less heat sink requirements, and smaller power supplies. The CS44600 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as A/V receivers, DVD receivers, digital speaker and automotive audio systems. ...
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... POWER SUPPLY, GROUNDING, AND PCB LAYOUT ....................................................................... 38 5.1 Reset and Power-Up ..................................................................................................................... 41 5.1.1 PWM PopGuard® Transient Control .................................................................................... 41 5.1.2 Recommended Power-Up Sequence ................................................................................... 41 5.1.3 Recommended PSR Calibration Sequence ........................................................................ 42 5.1.4 Recommended Power-Down Sequence .............................................................................. 43 6. REGISTER QUICK REFERENCE ........................................................................................................ 44 7. REGISTER DESCRIPTION .................................................................................................................. 48 7.1 Memory Address Pointer (MAP) .................................................................................................... 48 DS633F1 ......................................................................................................................... 16 ................................................................................................................ 19 ...................................................................................... 20 CS44600 3 ...
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... Increment (INCR) ................................................................................................................. 48 7.1.2 Memory Address Pointer (MAPx) ......................................................................................... 48 7.2 CS44600 I.D. and Revision Register (address 01h) (Read Only) ................................................. 48 7.2.1 Chip I.D. (Chip_IDx) ............................................................................................................. 48 7.2.2 Chip Revision (Rev_IDx) ...................................................................................................... 49 7.3 Clock Configuration and Power Control (address 02h) ................................................................. 50 7.3.1 Enable SYS_CLK Output (EN_SYS_CLK) ........................................................................... 50 7.3.2 SYS_CLK Clock Divider Settings (SYS_CLK_DIV[1:0]) ....................................................... 50 7 ...
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... Decimator Shift/Scale (addresses 35h, 36h, 37h) ....................................................................... 71 7.33.1 Decimator Shift (DEC_SHIFT[2:0]) ..................................................................................... 71 7.33.2 Decimator Scale (DEC_SCALE[18:0]) ............................................................................... 71 7.34 Decimator Outd (addresses 3Bh, 3Ch, 3Dh) ............................................................................... 72 7.34.1 Decimator Outd (DEC_OUTD[23:0]) .................................................................................. 72 8. PARAMETER DEFINITIONS ................................................................................................................ 73 9. REFERENCES ...................................................................................................................................... 75 10. PACKAGE DIMENSIONS 11. THERMAL CHARACTERISTICS ....................................................................................................... 77 12. ORDERING INFORMATION .............................................................................................................. 77 13. REVISION HISTORY .......................................................................................................................... 77 DS633F1 ......................................................................................................... 76 CS44600 5 ...
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... Figure 9.Control Port Timing - SPI Format ................................................................................................ 15 Figure 10.CS44600 Pinout Diagram ......................................................................................................... 16 Figure 11.Typical Full-Bridge Connection Diagram .................................................................................. 20 Figure 12.Typical Half-Bridge Connection Diagram .................................................................................. 21 Figure 13.CS44600 Data Flow Diagram (Single Channel Shown) ........................................................... 23 Figure 14.Fundamental Mode Crystal Configuration ................................................................................ 24 Figure 15.3rd Overtone Crystal Configuration .......................................................................................... 25 Figure 16.CS44600 Internal Clock Generation ......................................................................................... 25 Figure 17.I² ...
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... Table 12. Channel Load Compensation Filter Coarse Adjust ................................................................... 62 Table 13. Channel Load Compensation Filter Fine Adjust ........................................................................ 62 Table 14. PWM Minimum Pulse Width Settings ........................................................................................ 69 Table 15. Differential Signal Delay Settings .............................................................................................. 69 Table 16. Channel Delay Settings ............................................................................................................. 69 Table 17. Power Supply Sync Clock Divider Settings ............................................................................... 71 Table 18. Decimator Shift/Scale Coefficient Calculation Examples .......................................................... 72 DS633F1 CS44600 7 ...
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... PWM Interface VDP Serial Audio Interface VLS Control Interface VLC (Note PWM Interface V IND-PWM Serial Audio Interface V IND-S Control Interface V IND-C - -DQ T stg CS44600 Typ Max Units 2.5 2.63 V 2.5 2.63 V 3.3 3.47 V 5.0 5.25 V 3.3 3.47 V 5.0 5.25 V 2.5 2. ...
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... Serial Audio Interface Control Interface XTAL PWM Interface V IL Serial Audio Interface Control Interface PWM Interface Serial Audio Interface V OH Control Interface PWM Interface Serial Audio Interface V OL Control Interface I in include: SYS_CLK, DAI_MCLK, DAI_SCLK, DAI_LRCK, DAI_SDIN1-3 CS44600 Min Typ Max I - 150 - 1 150 - LS - ...
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... Idle Channel Noise / Signal-to-Noise Ratio Interchannel Isolation 11. Performance characteristics measured using filter shown in PWMOUTxx+ PWMOUTxx- Figure 1. Performance Characteristics Evaluation Active Filter Circuit 10 Symbol Min A-Weighted 102 unweighted unweighted (Note 11 THD+N - kHz) Figure - - + + - + CS44600 Typ Max Unit 108 - 99 105 - - -90 - 110 - - 100 - 1 ...
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... Frequency Response kHz -0 kHz -1 kHz - Fs = 44.1 kHz - kHz - Symbol Min t 18.518 clki t 8.34 clkih t 8.34 clkil 45 24.576 t t clkih clkil t clki Figure 2. XTI Timings CS44600 Typ Max Unit - 1.6 kHz - 24.0 kHz - 3.3 kHz - 44.5 kHz - +0. +0.02 dB (Note 14 ±0. ±0. ±0.09 ...
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... Figure 3. SYS_CLK Timings Symbol Min t 2.60 pwm VDP = 5 VDP = 3 VDP = 5 VDP = 3 pwm Figure 4. PWMOUTxx Timings Symbol Min t 592.576 psclki 45 t psclki Figure 5. PS_SYNC Timings CS44600 Typ Max Unit --- --- Typ Max Unit - 1.18 µ Typ Max Unit --- --- ...
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... DAI_SCLK High Time DAI_SCLK Low Time DAI_LRCK Setup Time Before DAI_SCLK Rising Edge DAI_SCLK Rising Edge Before DAI_LRCK Edge 15. After powering up, the CS44600, RST should be held low until after the power supplies and clocks are set- tled. 16. See Table 1 on page 26 17 ...
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... Repeated Start t high t t sud t sust hdd Figure 8. Control Port Timing - I²C Format CS44600 = 30 pF) L Min Max Unit - 100 kHz 4.7 - µs 4.0 - µs 4.7 - µs 4.0 - µs 4.7 - µ 250 ...
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... Data must be held for sufficient time to bridge the transition time of CCLK. 20. For f <1 MHz. sck CS CCLK CDIN CDOUT DS633F1 Symbol f sck t csh t css t scl t sch t dsu (Note 19 (Note 20 (Note 20 scl t sch t css dsu Figure 9. Control Port Timing - SPI Format CS44600 = 30 pF) L Min Typ Max Units 0 - 6.0 MHz µs 1 ...
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... PIN DESCRIPTIONS GND 1 PSR_EN 2 3 PS_SYNC GND 4 XTI 5 XTO 6 VDX 7 SYS_CLK 8 DAI_MCLK 9 DAI_SCLK 10 DAI_LRCK 11 DAI_SDIN1 12 DAI_SDIN2 13 DAI_SDIN3 VLS CS44600 Figure 10. CS44600 Pinout Diagram CS44600 GND 48 47 PWMOUTA3+ 46 PWMOUTA3- 45 VDP 44 PWMOUTB3+ PWMOUTB3 GND VDP GND 35 GPIO0 34 GPIO1 33 GPIO2 DS633F1 ...
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... RST condition. It can be configured as a general purpose input or output which can be individually controlled by the Host Controller. General Purpose Input, Output (Input/Output) - This pin is configured as an input follow- GPIO4 31 ing a RST condition. It can be configured as a general purpose input or output which can be individually controlled by the Host Controller. DS633F1 Pin Description CS44600 17 ...
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... PWM Interface Power (Input) - Determines the required signal level for the digital VDP 56, 62 input/output signals for the PWM and GPIO interface 18, 28, GND 36, 42, Digital Ground (Input) - Ground reference for digital circuits. 48, 53 CS44600 DS633F1 ...
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... V and 3.3/5.0 V TTL Compatible. 2.5-5.0 V, CMOS - - 2.5 V and 3.3/5.0 V TTL Compatible, Internal pull-down 3.3/5.0 V, 3.3/5.0 V TTL Compatible. CMOS/Open Drain 3.3/5.0 V, CMOS - 3.3/5.0 V, CMOS - 3.3/5.0 V, CMOS - - 3.3/5.0 V TTL Compatible, Internal pull-up. - 3.3/5.0 V TTL Compatible, Internal pull-up. 3.3/5.0 V, CMOS - 3.3/5.0 V, CMOS - 3.3/5.0 V, CMOS - CS44600 Receiver 19 ...
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... DAI_SDIN2 DAI_SDIN3 MUTE INT RST SCL/CCLK PS_SYNC SDA/CDOUT AD1/CDIN PSR_MCLK AD0/CS PSR_SYNC PSR_DATA PSR_EN PSR_RESET VLC GND CS44600 +3 +5.0 V PWM IN1 OUT1 Front Left CONTROL STATUS PWM IN2 OUT2 Front Right STATUS CONTROL PWM IN3 OUT3 Surr. Left CONTROL STATUS PWM IN4 OUT4 Surr ...
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... MUTE INT RST SCL/CCLK SDA/CDOUT PS_SYNC AD1/CDIN AD0/CS PSR_MCLK PSR_SYNC PSR_DATA VLC PSR_EN 0.1 µF PSR_RESET GND CS44600 +3 +5 µF PWM IN1 OUT1 Front Left PWM IN2 OUT2 Front Right CONTROL STATUS PWM IN1 OUT1 Surr. Left PWM IN2 OUT2 Surr. Right ...
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... This efficiency provides for a smaller device package, less heat sink requirements, and smaller power supplies. The CS44600 is ideal for audio systems requiring wide dynamic range, negligible distortion, and low noise such as A/V receivers, DVD receivers, digital speaker, and automotive audio systems. ...
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... Emphasis DAI_SCLK DAI_SDINx XTO XTAL / CLKIN XTI SYS_CLK 1,2,4,8 Figure 13. CS44600 Data Flow Diagram (Single Channel Shown) 4.3 Clock Generation The sources for internal clock generation for the PWM processing are as follows: • FsIn Domain: – DAI_MCLK, minimum 128Fs • FsOut Domain: – ...
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... FsOut Domain Clocking To ensure the highest quality conversion of PWM signals, the CS44600 is capable of operating from a rd fundamental mode MHz. If XTI is being directly driven by a clock signal, XTO can be left floating or tied to ground through a pull-down resistor and the internal oscillator should be powered down using the PDN_XTAL bit in register 02h ...
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... Y1 C3 Appropriate clock dividers for each functional block and a programmable divider to support an output for switched-mode power supply synchronization are provided. The clock generation for the CS44600 is shown in the Figure 16. XTO XTI SYS_CLK PS_SYNC DS633F1 Figure 15. 3 Overtone Crystal Configuration PWM Master ...
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... Digital Audio Input Port The CS44600 interfaces to an external Digital Audio Processor via the Digital Audio Input serial port, the DAI serial port. The DAI port has 3 stereo data inputs with support for I²S, left-justified and right-justified formats. The DAI port operates in slave operation only, where DAI_LRCK, DAI_SCLK and DAI_MCLK are always inputs ...
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... Bits/Sample DS633F1 + LSB MSB SCLK Rates 32, 48, 64, 128, 256 Fs 48, 64, 128, 256 Fs Figure 17. I²S Serial Audio Formats Left Channel + LSB MSB SCLK Rate(s) 32, 48, 64, 128, 256 Fs 48, 64, 128, 256 Fs Figure 18. Left-Justified Serial Audio Formats CS44600 nnel - LSB Right Channel - LSB 27 ...
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... Figure 20. One Line Mode #1 Serial Audio Format SCLK Rate(s) 32, 48, 64, 128, 256 Fs 48, 64, 128, 256 Fs 64 clks LSB MSB LSB MSB PWMOUTA3 PWMOUTB1 20 clks 20 clks CS44600 Right Channel clks Right Channels LSB MSB LSB MSB LSB PWMOUTB2 PWMOUTB3 20 clks 20 clks 1 0 MSB ...
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... MSB PWMOUTA3 PWMOUTB1 24 clks 24 clks 256 clks LSB MSB LSB MSB PWMOUTA3 PWMOUTB1 32 clks 32 clks 32 clks Figure 22. TDM Mode Serial Audio Format CS44600 128 clks Right Channels LSB MSB LSB MSB LSB PWMOUTB2 PWMOUTB3 24 clks 24 clks LSB MSB LSB MSB LSB ...
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... The supported DAI_MCLK to DAI_LRCK ratios are shown in 4.4.3 De-Emphasis The CS44600 includes on-chip digital de-emphasis filters. The de-emphasis feature is included to accom- modate older audio recordings that utilize pre-emphasis equalization as a means of noise reduction. Figure 23 shows the de-emphasis curve. The frequency response of the de-emphasis curve will scale pro- portionally with changes in sample rate, Fs ...
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... PWM switching frequency. The power stage external LC and snub- ber filter component values are based on this switching frequency. To accommodate input sample rates ranging from 32 kHz to 192 kHz the CS44600 utilizes a Sample Rate Converter (SRC) and several clock- ing modes that keep the PWM switching frequency fixed. ...
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... SZC[1:0] bits. 4.5.4 Peak Detect / Limiter The CS44600 has the ability to limit the maximum signal amplitude to prevent clipping. The Control Register (address 15h)” on page 60 eration. Peak Signal Limiting is performed by digital attenuation. The attack rate is determined by the iter Attack Rate (address 16h)” on page (address 17h)” ...
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... DS633F1 Quant Level OSRATE 64 1 384 421.875 64 2 Table 4. Typical PWM Switch Rate Settings and employs digital filtering to provide high quality interpolation. 69. CS44600 PWM Required XTAL Switch Rate or SYS_CLK (kHz) (MHz) 384 24.576 768 49.152 421.875 27.000 843.75 54.000 “PWM Configuration Table 4 ...
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... PWM modulator. All delays through the feedback path have been minimized such that the noise can- cellation is accomplished in real-time allowing for substantial noise rejection within the output audio signal. See “Typical Connection Diagrams” on page 22 (CS4461) to the CS44600 for PSR feedback, and the CS4461 datasheet. 34 for examples on how to connect the external ADC “ ...
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... The control port has 2 modes: SPI and I²C, with the CS44600 acting as a slave device. SPI mode is selected if there is a high to low transition on the AD0/CS pin, after the RST pin has been brought high. I²C mode is selected by connecting the AD0/CS pin through a resistor to VLC or GND, thereby permanently selecting the desired AD0 bit address state ...
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... All other transitions of SDA occur while the clock is low. The first byte sent to the CS44600 after a Start condition consists bit chip address field and a R/W bit (high for a read, low for a write). The upper 5 bits of the 7-bit address field are fixed at 10011. To communicate with a CS44600, the chip address field, which is the first byte sent to the CS44600, should match 10011 followed by the settings of the AD1 and AD0 ...
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... Host Interrupt The CS44600 has a comprehensive interrupt capability. The INT output pin is intended to drive the inter- rupt input pin on the host microcontroller. The INT pin may be set to be active low, active high or active low with an open-drain driver. This last mode is used for active low, wired-OR hook-ups, with multiple pe- ripherals connected to the microcontroller interrupt input pin. Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. See “ ...
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... POWER SUPPLY, GROUNDING, AND PCB LAYOUT The CS44600 requires a 2.5 V digital power supply for the core logic. In order to support a number of PWM backend solutions, separate VDP power pins are provided to condition the interface signals to support up to 5.0 V levels. The VDP power pins control the voltage levels for all PWM interface signals, PSR interface signals and GPIO for control and status ...
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... L1 and C5 are only used for 3 overtone crystals. C3 and C4 should have a C0G (NPO) dielectric. Care should be taken to minimize the distance between the CS44600 XTI/XTO pins and C3. Top and bottom ground fill should be used as much as possible around and in between all crystal circuit components to minimize noise. ...
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... CS4461 AIN+/- pins. The CS4461 and input buffer should be placed on the board between the CS44600 and the high voltage power supply. The sense point of the high volt- age power supply (the point at which the input buffer taps off of the high voltage power supply) should be close to the middle of the amplifier output channels ...
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... When RST is low, the CS44600 enters a low-power mode and all internal states are reset, including the control port and registers. When RST is high, the control port becomes operational and the desired settings should be loaded into the control registers ...
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... Set MIN_PULSE[4:0] to ‘00000’b. 7. Set the PDN bit to ‘0’b to take the CS44600 out of the power-down state. 8. Start all clocks on the DAI interface (DAI_MCLK, DAI_SCLK, DAI_LRCK). This will initiate the SRC to begin the lock sequence ...
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... Concurrently with the ramp-down sequence, if desired, stop all clocks on the DAI interface (DAI_MCLK, DAI_SCLK, DAI_LRCK). 8. Set the PDN bit to ‘1’b to put the CS44600 in the power down state. DS633F1 Set PSR_RESET = 1b ...
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REGISTER QUICK REFERENCE Addr Function 7 6 01h ID / Rev. CHIP_ID3 CHIP_ID2 page 48 default 1 1 Clock Config / Power EN_SYS_CLK SYS_CLK_DIV1 02h Control page 49. default 1 0 RESERVED RESERVED 03h Chnl Power Down page 50. ...
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Addr Function 7 6 Channel Vol. Con- CHB2_FVOL1 CHB2_FVOL0 11h trol 1-Fraction page 57. default 0 0 RESERVED RESERVED Channel Vol. Con- 12h trol 2-Fraction page 57 default 0 0 13h Channel Mute RESERVED RESERVED page 58 default 0 0 ...
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Addr Function 7 6 Chnl A3 Comp. RESERVED RESERVED 21h Filter - Fine Adj page 61 default 0 0 Chnl B3 Comp. RESERVED RESERVED 22h Filter - Coarse Adj page 60 default 0 0 Chnl B3 Comp. RESERVED RESERVED 23h ...
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Addr Function 7 6 PWM Minimum Pulse DISABLE_ RESERVED 32h Width PWMOUTxx- page 67 default 0 0 33h PWMOUT Delay DIFF_DLY2 DIFF_DLY1 page 68 default 0 0 PSR / Power Supply PSR_EN PSR_RESET 34h Config page 69 default 0 0 ...
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... CS44600 I.D. and Revision Register (address 01h) (Read Only CHIP_ID3 CHIP_ID2 CHIP_ID1 7.2.1 Chip I.D. (Chip_IDx) Default = 1101 Function: I.D. code for the CS44600. Permanently set to 1101. 7.2.2 Chip Revision (Rev_IDx) Default = 0001 Function: CS44600 revision level. Revision A is coded as 0001 MAP4 MAP3 CHIP_ID0 REV_ID3 CS44600 2 1 ...
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... XTI input, this bit should be set to ‘1’b. DS633F1 4 3 PWM_MCLK_DIV1 PWM_MCLK_DIV0 PDN_XTAL PDN_OUTPUT_MODE PDN SYS_CLK Clock Divider 00 Use state of MUTE input pin following RST condition 01 Divide Divide Divide by 8 PWM_MCLK_DIV[1:0] PWM Master Clock Divider 00 Divide Divide Divide Divide by 8 CS44600 ...
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... When transitioning from normal operation to power down, the specific chan- nel will power down according to the state of the RAMP[1:0] bits and the channel output configuration se- lected. Ramp control is found PDN_PWMA3 PDN_PWMB2 “Ramp Configuration (address 05h)” on page CS44600 PDN_PWMA2 PDN_PWMB1 PDN_PWMA1 54. DS633F1 ...
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... FREEZE bit. DS633F1 RESERVED AM_FREQ_HOP DIF0 Description 0 Left-Justified 24-bit data 1 I² 24-bit data 0 Right-Justified, 16-bit data 1 Right-Justified, 24-bit data 0 One-Line mode #1, 20-bit data 1 One-Line mode #2, 24-bit data 0 TDM Mode 32-bit data Table 5. Digital Audio Interface Formats CS44600 FREEZE DEM1 DEM0 Figure ...
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... The Ramp Speed sets the time for the PWM signal to linearly ramp-up and down from the bias point (50% PWM duty cycle). Refer to Section 5.1 RAMP1 RAMP0 “Recommended Power-Up Sequence” on page 43 45. CS44600 RESERVED RAMP_SPD1 RAMP_SPD0 and “Recommended Power- DS633F1 ...
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... Enable 50% Duty Cycle for Mute Condition (MUTE_50/50) Default = Disabled 1 - Enabled Function: This bit enables the modulator to output an exact 50%-duty-cycle PWM signal (not modulated), which cor- responds to digital silence, for all mute conditions. The muting function is affected, similar to volume con- DS633F1 RESERVED MUTE_50/50 CS44600 SRD_ERR SRU_ERR AMUTE 53 ...
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... Enabled Function: The PWM converters of the CS44600 will mute the output following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The muting function is affected, similar to volume control changes, by the Soft and Zero Cross bits (SZC[1:0]) ...
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... Select the bit representation of the desired 0.25 fractional increment. This is MSTR_FVOL[1:0]. To calculate from a negative decimal integer:fraction value to a binary, 2’s complement integer:fraction value, do the following: DS633F1 MSTR_IVOL4 MSTR_IVOL3 Hex Value Table 6. Master Integer Volume Settings RESERVED RESERVED CS44600 2 1 MSTR_IVOL2 MSTR_IVOL1 MSTR_IVOL0 Volume Setting + -127 RESERVED MSTR_FVOL1 MSTR_FVOL0 ...
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... MSTR_FVOL(1: Table 7. Master Fractional Volume Settings CS44600 Volume Setting +24.00 dB +23.50 dB +1.75 dB +1.00 dB +0. -0.50 dB -1.00 dB -1.25 dB -2.50 dB -126.00 dB -126.25 dB -127.00 dB DS633F1 ...
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... Volume Control - Fraction (address 08h)” on page 57 bers to 2’s complement binary values. DS633F1 CHXX_IVOL4 CHXX_IVOL3 Hex Value Table 8. Channel Integer Volume Settings CHA2_FVOL0 CHB1_FVOL1 RESERVED CHB3_FVOL1 CS44600 CHXX_IVOL2 CHXX_IVOL1 CHXX_IVOL0 Volume Setting + -127 CHB1_FVOL0 CHA1_FVOL1 CHA1_FVOL0 CHB3_FVOL0 CHA3_FVOL1 CHA3_FVOL0 ...
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... RESERVED CHB3_MUTE 7.13.1 Independent Channel Mute (CHXX_MUTE) Default = Disabled 1 - Enabled Function: The PWM outputs of the CS44600 will mute when enabled. The muting function is affected, similar to at- tenuation changes, by the Soft and Zero Cross bits (SZC[1:0]). 7.14 Channel Invert (address 14h RESERVED ...
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... Peak Signal Limiter Enable (LIMIT_EN) Default = Disabled 1 - Enabled Function: The CS44600 will limit the maximum signal amplitude to prevent clipping when this function is enabled. Peak Signal Limiting is performed by digital attenuation. The attack rate is determined by the Limiter At- tack Rate register. 7.16 Limiter Attack Rate (address 16h) ...
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... Release Rate - 384 kHz 1 (µs per / dB 1333.333 20 66.667 40 33.333 60 22.222 90 14.815 Table 11. Limiter Release Rate Settings CHXX_CORS4 CHXX_CORS3 CS44600 Attack Rate - 421.875 kHz 1 (µs per / dB) 8 75.852 3.793 1.896 1.264 0.843 2 1 RRATE2 RRATE1 RRATE0 15h)). Release Rate - 421.875 kHz 1 (µs per / ...
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... CHXX_CORS[5:0] Coarse Filter Setting 000000 0 dB 000001 -0.1 dB 001010 -1.0 dB 011001 -2.5 dB 100000 -3.2 dB 101000 -4 CHXX_FINE4 CHXX_FINE3 CHXX_FINE[5:0] Fine Filter Setting 000000 0 dB 000001 -0.1 dB 001010 -1.0 dB 011001 -2.5 dB 100000 -3.2 dB 101000 -4 RESERVED RESERVED CS44600 CHXX_FINE2 CHXX_FINE1 CHXX_FINE0 RESERVED RESERVED OVFL_L/E 61 ...
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... Interrupt Status Register. Only the last valid state of the SRC will be reported RMPDN_DONE MUTE_DONE only when the interrupt type is set to “edge trigger”. If either of these interrupt CS44600 M_OVFL_INT RESERVED RESERVED 2 1 OVFL_INT GPIO_INT RESERVED only when the in- “ ...
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... The GPIO Status Register must be read to clear this interrupt. If the GPIO input is configured as “edge trigger” the interrupt will clear. If the GPIO input is configured as “level sensitive”, the interrupt condition will remain as long as the GPIO input remains at the active level. DS633F1 CS44600 55. 63 ...
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... General Purpose Input - If the pin is configured as an input, this bit defines the input polarity (0 = Active Low Active High). General Purpose Output - If the pin is configured as a general purpose output, this bit defines the GPIO output type (0 = CMOS OPEN-DRAIN CHA3_OVFL CHB2_OVFL GPIO4_I/O GPIO3_I GPIO4_P/T GPIO3_P/T CS44600 CHA2_OVFL CHB1_OVFL CHA1_OVFL GPIO2_I/O GPIO1_I/O GPIO0_I GPIO2_P/T GPIO1_P/T GPIO0_P/T DS633F1 ...
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... General Purpose Output - For GPIO pins configured as outputs, these bits are used to control the output signal level written to a particular bit will cause the corresponding GPIO pin to be driven to a logic high will cause a logic low. DS633F1 GPIO4_L/E GPIO3_L CS44600 GPIO2_L/E GPIO1_L/E GPIO0_L ...
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... A2 and B2. This parameter can only be changed when all modulators and associated logic are in the pow RESERVED M_GPIO3 1b. Attempts to write this register while the PDN is not set will be ignored. “Clock Configuration and Power Control (address 02h)” CS44600 M_GPIO2 M_GPIO1 M_GPIO0 RESERVED “ ...
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... PDN bit in the register DS633F1 “Clock Configuration and Power Control (address 02h)” “Clock Configuration and Power Control (address 02h)” “Clock Configuration and Power Control (address 02h)” MIN_PULSE2 “Clock Configuration and Power Control (address 02h)” on CS44600 MIN_PULSE1 MIN_PULSE0 “Clock Configuration and 67 ...
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... Configuration and Power Control (address Binary Code Delay Setting (multiply by PWM_MCLK period) 000 delay 001 1 100 4 111 7 Table 15. Differential Signal Delay Settings to a 1b. Attempts to write this register while the Delay Setting(multiply by PWM_MCLK period delay Table 16. Channel Delay Settings CS44600 CHNL_DLY2 CHNL_DLY1 CHNL_DLY0 “Clock Con- DS633F1 ...
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... A ‘0’b in this bit will cause the PSR_EN to drive a logic low. A ‘1’b will drive a logic high. DS633F1 tdif dly tch dly tdif dly tdif dly tch dly tdif dly tdif dly tch dly tdif dly Figure 31. PWM Output Delay RESERVED RESERVED PS_SYNC_DIV2 CS44600 1 0 PS_SYNC_DIV1 PS_SYNC_DIV0 69 ...
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... Divide by 32 010 Divide by 64 011 Divide by 128 100 Divide by 256 101 Divide by 512 110 Divide by 1024 DEC_SHIFT0 RESERVED (Decimator Outd (addresses 3Bh, 3Ch, “Recommended PSR Calibration Sequence” on page CS44600 2 1 DEC_SCALE18 DEC_SCALE17 DEC_SCALE16 3Dh)) dur- Decimator Scale DS633F1 44. ...
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... Outd (addresses 3Bh, 3Ch, “Recommended PSR Calibration Sequence” on page DEC_SHIFT[2:0] Calculated Coefficient (C 001b=1 0.5*2^(1)=1 010b=2 0.6331*2^(2)=2.5325 DEC_OUTD20 DEC_OUTD19 DEC_OUTD12 DEC_OUTD11 DEC_OUTD04 DEC_OUTD03 44. CS44600 3Dh)) dur- Decimator Shift ) PSR DEC_OUTD18 DEC_OUTD17 DEC_OUTD16 DEC_OUTD10 DEC_OUTD09 DEC_OUTD08 DEC_OUTD02 DEC_OUTD01 DEC_OUTD00 44. ...
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... FS is defined as dB relative to full-scale. The “A” indicates an A weighting filter was used. Differential Nonlinearity The worst case deviation from the ideal code width. Units in LSB. FFT Fast Fourier Transform. Fs Sampling Frequency. Resolution The number of bits in the output words to the DACs, and in the input words to the ADCs. 72 CS44600 DS633F1 ...
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... It is measured over kHz bandwidth with units in dB. SRC Sample Rate Converter. Converts data derived at one sample rate to a differing sample rate. The CS44600 operates at a fixed sample frequency. The internal sample rate converter is used to convert digital audio streams playing back at other frequencies to the PWM output rate ...
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... BSC 0.484 0.393 BSC 0.398 0.472 BSC 0.484 0.393 BSC 0.398 0.020 BSC 0.024 0.024 0.030 4° 7.000° CS44600 Note: See Legend Below A A1 MILLIMETERS MIN NOM MAX --- 1.40 1.60 0.05 0.10 0.15 0.17 0.20 0.27 11 ...
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... Half-Bridge Connection Diagram” on page 23 Figure 13 on page 23 Section 7.5.2 "AM Frequency Hopping (AM_FREQ_HOP)" on page 51 “Ordering Information” on page 75 CS44600 Min Typ Max Units - 48 - °C/Watt - 38 - Order# Rail CS44600-CQZ Tape and CS44600-CQZR Reel Rail CS44600-DQZ Tape and CS44600-DQZR Reel - - CDB44800 - - CRD44800 - - CRD44800-ST- CRD44600-PH-FB 75 ...
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... Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. I² registered trademark of Philips Semiconductor. 76 www.cirrus.com. CS44600 DS633F1 ...