CS44600-CQZ Cirrus Logic Inc, CS44600-CQZ Datasheet - Page 29

• Manufacturer Part Number: CS44600-CQZ
• Description: IC AMP CTLR DGTL 6CH 64LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Digital Amplifier Controllerr

Specifications of CS44600-CQZ

• Package / Case: 64-LQFP
• Applications: Automotive Systems
• Mounting Type: Surface Mount
• Thd Plus Noise: 0.05 %
• Operating Supply Voltage: 2.5 V
• Supply Current: 150 mA
• Maximum Power Dissipation: 387 mW
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Supply Type: Digital
• Supply Voltage (max): 2.62 V
• Supply Voltage (min): 2.37 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1023 - EVAL BOARD FOR CS44600
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1068-5

DS633F1
DAI_SDIN1
DAI_LRCK
DAI_SCLK
DAI_SDIN1
DAI_LRCK
DAI_SCLK
4.4.1.5
4.4.1.6
In One Line mode #2 format, data is received most significant bit first on the first DAI_SCLK after a
DAI_LRCK transition and is valid on the rising edge of DAI_SCLK. DAI_SCLK must operate at a 256 Fs
rate. DAI_LRCK identifies the start of a new frame and is equal to the sample period. DAI_LRCK is sam-
pled as valid on the same clock edge as the most significant bit of the first data sample and must be held
high for 128 DAI_SCLK periods. Each time slot is 24 bits wide, with the valid data sample left-justified with-
in the time slot. Valid data lengths are 16, 18, 20, or 24 bits. Valid samples rates for this mode are 32 kHz
to 96 kHz.
In TDM mode format, data is received most significant bit first on the first DAI_SCLK after a DAI_LRCK
transition and is valid on the rising edge of DAI_SCLK. DAI_SCLK must operate at a 256 Fs rate.
DAI_LRCK identifies the start of a new frame and is equal to the sample period. DAI_LRCK is sampled
as valid on the proceeding clock edge as the most significant bit of the first data sample and must be held
valid for at least 1 DAI_SCLK period. Each time slot is 32 bits wide, with the valid data sample left-justified
within the time slot. Valid data lengths are 16, 18, 20, 24 or 32 bits. Valid samples rates for this mode are
32 kHz to 96 kHz.
MSB
MSB
PWMOUTA1
PWMOUTA1
24 clks
32 clks
One Line Mode #2
TDM Mode
LSB
LSB
MSB
MSB
PWMOUTA2
PWMOUTA2
32 clks
Left Channels
Figure 21. One Line Mode #2 Serial Audio Format
24 clks
128 clks
LSB
Figure 22. TDM Mode Serial Audio Format
LSB
MSB
PWMOUTA3
MSB
32 clks
PWMOUTA3
24 clks
LSB
LSB
32 clks
256 clks
MSB
PWMOUTB1
MSB
24 clks
PWMOUTB1
32 clks
LSB
LSB
MSB
MSB
PWMOUTB2
PWMOUTB2
Right Channels
24 clks
32 clks
128 clks
LSB
LSB
MSB
MSB
PWMOUTB3
PWMOUTB3
32 clks
24 clks
LSB
LSB
CS44600
32 clks
MSB
29