AD5024 Analog Devices, AD5024 Datasheet - Page 9

• Manufacturer Part Number: AD5024
• Manufacturer: Analog Devices

Specifications of AD5024

• Resolution (bits): 12bit
• Dac Update Rate: 125kSPS
• Dac Settling Time: 8µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

Table 7. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic
LDAC
SYNC
V
V
V
V
V
POR
V
CLR
V
V
V
GND
DIN
SCLK
DD
REF
REF
OUT
OUT
REF
REF
OUT
OUT
B
A
C
D
A
C
D
B
Description
LDAC can be operated in two modes, asynchronously and synchronously, as shown in
this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows
all DAC outputs to simultaneously update. This pin can also be tied permanently low in standalone mode.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes
low, it powers on the SCLK and DIN buffers and enables the shift register. Data is transferred in on the
falling edges of the next 32 clocks. If SYNC is taken high before the 32
SYNC acts as an interrupt and the write sequence is ignored by the device.
Power Supply Input. These parts can be operated from 4.5 V to 5.5 V, and the supply should be decoupled
with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
DAC B Reference Input. This is the reference voltage input pin for DAC B.
DAC A Reference Input. This is the reference voltage input pin for DAC A.
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Power-On Reset. Tying this pin to GND powers up the part to 0 V. Tying this pin to V
part to midscale.
DAC C Reference Input. This is the reference voltage input pin for DAC C.
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are
ignored. When CLR is activated, the input register and the DAC register are updated with the data
contained in the clear code register—zero, midscale, or full scale. Default setting clears the output to 0 V.
DAC D Reference Input. This is the reference voltage input pin for DAC D.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the shift register on the
falling edge of the serial clock input.
Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data
can be transferred at rates of up to 50 MHz.
Figure 7. 16-Lead TSSOP (RU-16) Pin Configuration
V
V
V
V
LDAC
SYNC
REF
REF
OUT
OUT
POR
V
DD
B
A
A
C
1
2
3
4
5
6
7
8
Rev. E | Page 9 of 28
(Not to Scale)
AD5024/
AD5044/
AD5064
TOP VIEW
16
15
14
13
12
11
10
9
SCLK
DIN
GND
V
V
V
CLR
V
OUT
OUT
REF
REF
D
C
B
D
AD5024/AD5044/AD5064
nd
falling edge, the rising edge of
DD
Figure 4
powers up the
. Pulsing