CS8415A-CZZ Cirrus Logic Inc, CS8415A-CZZ Datasheet - Page 33

• Manufacturer Part Number: CS8415A-CZZ
• Description: IC 96KHZ DGTL RCVR 28-TSSOP
• Manufacturer: Cirrus Logic Inc
• Type: Digital Audio Interface Receiverr

Specifications of CS8415A-CZZ

• Applications: Automotive Audio
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Audio Control Type: Digital
• Control Interface: I2C, Serial
• Control / Process Application: AV & DVD Receivers, CD-R, Digital Mixing Consoles
• Supply Voltage Range: 2.85V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1122-5

DS470F4
11.PIN DESCRIPTION - HARDWARE MODE
COPY
VL2+
VL+
VL3+
EMPH
RXP0
RXN0
VA+
AGND
FILT
RST
Pin Name
23
27
# Pin Description
1
2
3
4
5
6
7
8
9
COPY Channel Status Bit (Output) - Reflects the state of the Copyright Channel Status bit in the incoming
AES3 data stream. If the category code is set to General, copyright will be indicated whatever the state of
the Copyright bit.
Positive Digital Power (Input) - Typically +3.3 V or +5.0 V.
Pre-Emphasis (Output) - EMPH
emphasis.
sis other than 50/15 ms. This pin is also a start-up option which, along with ORIG, determines the serial port
format. A 47 kΩ resistor to either VL+ or DGND is required.
AES3/SPDIF Receiver Port (Input) - Differential line receiver inputs for the AES3 biphase encoded data.
See Appendix A for recommended circuits.
Positive Analog Power (Input) - Nominally +5.0 V. This supply should be as quiet as possible since noise
on this pin will directly affect the jitter performance of the recovered clock.
Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be connected
to a common ground area under the chip.
PLL Loop Filter (Output) - An RC network should be connected between this pin and ground. See
dix C: PLL Filter” on page 41
Reset (Input) - When RST is low, the CS8415A enters a low power mode and all internal states are reset.
On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in
frequency and phase. This is particularly true in hardware mode with multiple CS8415A devices where syn-
chronization between devices is important.
EMPH
is high when the Channel Status data indicates no pre-emphasis or indicates pre-empha-
for recommended schematic and component values.
is low when the incoming Channel Status data indicates 50/15 ms pre-
CS8415A
“Appen-
33