AD9780 Analog Devices, AD9780 Datasheet - Page 24

• Manufacturer Part Number: AD9780
• Description: Dual 12-Bit, LVDS Interface 500 MSPS DAC
• Manufacturer: Analog Devices

Specifications of AD9780

• Resolution (bits): 12bit
• Dac Update Rate: 500MSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9780/AD9781/AD9783
PARALLEL DATA PORT INTERFACE
The parallel port data interface consists of up to 18 differential
LVDS signals, DCO, DCI, and up to 16 data lines (D[15:0]), as
shown in Figure 56. DCO is the output clock generated by the
AD9780/AD9781/AD9783 that is used to clock out the data
from the digital data engine. The data lines transmit the multip-
lexed I and Q data words for the I and Q DACs, respectively.
DCI provides timing information about the parallel data and
signals the I/Q status of the data.
As diagrammed in Figure 56, the incoming LVDS data is
latched by an internally generated clock referred to as the data
sampling signal (DSS). DSS is a delayed version of the main
DAC clock signal, CLKP/CLKN. Optimal positioning of the
rising and falling edges of DSS with respect to the incoming
data signals results in the most robust transmission of the DAC
data. Positioning the edges of DSS with respect to the data
signals is achieved by selecting the value of a programmable
delay element, SMP. A procedure for determining the optimal
value of SMP is given in the Optimizing the Parallel Port
Timing section.
In addition to properly positioning the DSS edges, maximizing
the opening of the eye in the clock input (DCIP/DCIN) and
data signals improves the reliability of the data port interface.
The two sources of degradation that reduce the eye in the clock
input and data signals are the jitter on these signals and the
skew between them. Therefore, it is recommended that the clock
input signals be generated in the same manner as the data
signals with the same output driver and data line routing. In
other words, it should be implemented as a 17
an alternating (010101 …) bit sequence.
D15:D0
DCIP/DCIN
DCOP/DCON
Figure 56. Digital Data Port Block Diagram
DSS
HLD_DLY
SET_DLY
FF
FF
SMP_DLY
DDSS
DDCI
RETIMING
DEMUX
AND
FF
SEEK
DISTRIBUTION
Q DAC
I DAC
th
CLOCK
data line with
CLK
Rev. A | Page 24 of 36
OPTIMIZING THE PARALLEL PORT TIMING
Before outlining the procedure for determining the delay for
SMP (that is, the positioning of DSS with respect to the data
signals), it is worthwhile to describe the simplified block
diagram of the digital data port. As can be seen in Figure 57, the
data signals are sampled on the rising and falling edges of DSS.
From there, the data is demultiplexed and retimed before being
sent to the DACs.
The clock input signal provides timing information about the
parallel data, as well as indicating the destination (that is, I DAC
or Q DAC) of the data. A delayed version of DCI is generated
by a delay element, SET, and is referred to as DDCI. DDCI is
sampled by a delayed version of the DSS signal, labeled as DDSS
in Figure 56. DDSS is simply DSS delayed by a period of time,
HLD. The pair of delays, SET and HLD, allows accurate timing
information to be extracted from the clock input. Increasing the
delay of the HLD block results in the clock input being sampled
later in its cycle. Increasing the delay of the SET block results in
the clock input being sampled earlier in its cycle. The result of
this sampling is stored and can be queried by reading the SEEK
bit. Because DSS and the clock input signal are the same
frequency, the SEEK bit should be a constant value. By varying
the SET and HLD delay blocks and seeing the effect on the
SEEK bit, the setup-and-hold timing of DSS with respect to
clock input (and, hence, data) can be measured.
The incremental units of SET, HLD, and SMP are in units of
real time, not fractions of a clock cycle. The nominal step size
for SET and HLD is 80 ps. The nominal step size for SMP is
160 ps. Note that the value of SMP refers to Register 0x05,
Bits[4:0], SET refers to Register 0x04, Bits[7:4], and HLD refers
to Register 0x04, Bits[3:0].
A procedure for configuring the device to ensure valid sampling
of the data signals follows. Generally speaking, the procedure
begins by building an array of setup-and-hold values as the sample
delay is swept through a range of values. Based on this infor-
mation, a value of SMP is programmed to establish an optimal
sampling point. This new sampling point is then double-checked
to verify that it is optimally set.
DCIP/DCIN
DATA
DSS
SAMPLE 1
Figure 57. Timing Diagram of Parallel Interface
I0
SAMPLE 2
Q0
t
HLD0
SAMPLE 3
I1
SAMPLE 4
t
Q1
HLD0
SAMPLE 5
I2
SAMPLE 6
Q2