AD9704 Analog Devices, AD9704 Datasheet
AD9704
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AD9704 Summary of contents
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... The AD9704/AD9705/AD9706/AD9707 family in the TxDAC series of high performance, CMOS digital-to- analog converters (DACs). This pin-compatible, 8-/10-/12-/14-bit resolution family is optimized for low power operation, while maintaining excellent dynamic performance. The AD9704/ AD9705/AD9706/AD9707 family is pin-compatible with the AD9748/AD9740/AD9742/AD9744 family of TxDAC converters and is specifically optimized for the transmit signal path of communication systems ...
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... ESD Caution................................................................................ 11 Pin Configurations and Function Descriptions ......................... 12 AD9707 ........................................................................................ 12 AD9706 ........................................................................................ 13 AD9705 ........................................................................................ 14 AD9704 ........................................................................................ 15 Typical Performance Characteristics ........................................... 16 AD9707 ........................................................................................ 16 AD9704, AD9705, and AD9706............................................... 23 REVISION HISTORY 10/11—Rev Rev. B Changes to Features Section............................................................ 1 Changes to Table 1............................................................................ 5 Changes to Table 2............................................................................ 6 Changes to Table 4............................................................................ 8 Changes to Table 5............................................................................ 9 Changes to Figure 3 and Table 9................................................... 12 Changes to Figure 4 and Table 10 ...
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... Changes to Table 4 ............................................................................7 Changes to Table 6 ............................................................................9 Changes to Figure 17 and Figure 18 .............................................16 Deleted Figure 29, Renumbered Sequentially .............................19 Changes to Figure 44 ......................................................................22 Changes to Figure 57 Caption .......................................................25 AD9704/AD9705/AD9706/AD9707 Changes to Figure 73, Figure 75, and Figure 77..........................31 Changes to Table 16 ........................................................................32 Replaced Single-Ended Buffered Output Using an Op Amp Section ....................................................................................40 Changes to Figure 91 ......................................................................41 Changes to Figure 93 ...
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... AD9704/AD9705/AD9706/AD9707 FUNCTIONAL BLOCK DIAGRAM 0.1µF 1. SET 3.6V CLK+ CLK– 1.7V TO 3.6V 1.7V TO 3.6V AVDD ACOM 1.0V REF AD9707 REFIO CURRENT SOURCE FS ADJ ARRAY CLKVDD SEGMENTED LSB CLKCOM SWITCHES SWITCHES LATCHES SPI DVDD DCOM DIGITAL INPUTS (DB13 TO DB0) SLEEP/CSB Figure 1. Rev Page Data Sheet ...
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... Rev Page AD9704/AD9705/AD9706/AD9707 AD9705 AD9704 Min Typ Max Min Typ 10 8 ±0.10 ±0.36 ±0.03 ±0.10 ±0.09 ±0.31 ±0.02 ±0.03 −0.03 0 +0.03 −0.03 0 −2.7 −0.1 +2.7 −2.7 −0.1 −2.7 −0.1 +2.7 −2.7 −0 −0.8 +0.8 −0.8 200 ...
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... Rev Page AD9705 AD9704 Min Typ Max Min Typ 0.7 7.5 0.7 0.6 1 0.6 42.5 64 42.5 −0.2 +0.03 +0.2 −0.2 +0.03 −40 +85 −40 AD9705 AD9704 Max Min Typ Max Min Typ 175 175 2.5 2.5 2.5 2 ...
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... OUTFS AD9707 AD9706 Min Typ Max Min Typ Max 2 0.9 0 0.9 −10 +10 −10 + 1.4 1.4 0.3 0.3 1.6 1.6 0.6 0.6 2.8 2 0.75 1.5 2.25 0.75 1.5 2.25 0.5 1.5 0.5 1.5 Rev Page AD9704/AD9705/AD9706/AD9707 AD9705 AD9704 Min Typ Max Min Typ 2 0.9 0 −10 +10 − 1.4 1.4 0.3 0.3 1.6 1.6 0.6 0.6 2.8 2 0.75 1.5 2.25 0.75 1.5 0.5 1.5 0.5 1.5 Max Unit V 0.9 V +10 μA 10 μ ...
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... Rev Page AD9705 AD9704 Min Typ Max Min Typ 10 8 ±0.10 ±0.36 ±0.03 ±0.09 ±0.30 ±0.02 −0.03 0 +0.03 −0.03 0 −2.7 −0.2 +2.7 −2.7 −0 2 −0.8 +0.8 −0.8 200 200 5 5 0.98 1.025 1.08 0.98 1.025 100 100 0.1 1.25 0.1 10 ...
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... Rev Page AD9704/AD9705/AD9706/AD9707 AD9705 AD9704 Min Typ Max Min Typ −2 −0.1 +2 −2 −0.1 −40 +85 −40 AD9705 AD9704 Max Min Typ Max Min Typ 125 125 11 11 5.6 5 2.5 2.5 2.5 2 ...
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... Typ 1.2 1.8 1.2 1.8 0 0.5 0 −10 +10 −10 + 2.3 2 2.4 2.4 0.1 0.1 6.2 6.2 0 1.8 0 0.4 0.9 1.3 0.4 0.9 0.5 1.5 0.5 1 LPW IOUTA OR IOUTB 0.1% Figure 2. Timing Diagram Rev Page AD9705 AD9704 Max Min Typ Max Min 1.2 1.8 1.2 0.5 0 0.5 +10 −10 +10 −10 +10 +10 5 2.3 2 2.4 2.4 0.1 0.1 6.2 6.2 1.8 0 1.8 0 1.3 0.4 0.9 1.3 0.4 0.5 1.5 0.5 H 0.1% Data Sheet Typ Max Unit 1 0.5 V +10 μ ...
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... Storage Temperature Range −65°C to +150°C Lead Temperature (10 sec) 300°C AD9704/AD9705/AD9706/AD9707 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied ...
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... AD9704/AD9705/AD9706/AD9707 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS AD9707 Table 9. AD9707 Pin Function Descriptions Pin No. Mnemonic Description 28 to 32, 1, DB12 to DB1 Data Bit 12 to Data Bit DVDD Digital Supply Voltage (1 3.6 V). 9 DB0 (LSB) Least Significant Data Bit (LSB). 10, 26 DCOM Digital Common ...
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... Scale) DB0 (LSB AVDD PIN/SPI/RESET NOTES CONNECT. DO NOT CONNECT TO THIS PIN RECOMMENDED THAT THE EXPOSED PAD BE THERMALLY CONNECTED TO A COPPER GROUND PLANE FOR ENHANCED ELECTRICAL AND THERMAL PERFORMANCE. Figure 4. AD9706 Pin Configuration Rev Page AD9704/AD9705/AD9706/AD9707 ...
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... AD9704/AD9705/AD9706/AD9707 AD9705 Table 11. AD9705 Pin Function Descriptions Pin No. Mnemonic Description 28 to 32, DB8 to DB1 Data Bit 8 to Data Bit DVDD Digital Supply Voltage (1 3.6 V). 5 DB0 (LSB) Least Significant Data Bit (LSB Connect. 10, 26 DCOM Digital Common. 11 CLKVDD Clock Supply Voltage (1 ...
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... Data Sheet AD9704 Table 12. AD9704 Pin Function Descriptions Pin No. Mnemonic Description 28 to 32, 1 DB6 to DB1 Data Bit 6 to Data Bit 1. 2 DB0 (LSB) Least Significant Data Bit (LSB). 3 DVDD Digital Supply Voltage (1 3.6 V Connect. 10, 26 DCOM Digital Common. ...
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... AD9704/AD9705/AD9706/AD9707 TYPICAL PERFORMANCE CHARACTERISTICS AD9707 VDD = 3 mA, unless otherwise noted. OUTFS 10MSPS CLOCK 65MSPS CLOCK 175MSPS 70 CLOCK 125MSPS 60 CLOCK (MHz) OUT Figure 7. SFDR vs. f OUT ...
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... CLOCK = 175MSPS CLOCK – OUT CLOCK 175MSPS dBFS Figure 18. Dual-Tone IMD vs. Lower f Rev Page AD9704/AD9705/AD9706/AD9707 –120 –125 –130 –135 1mA –140 2mA –145 –150 5mA –155 –160 –165 FREQUENCY (MHz) Figure 16 ...
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... AD9704/AD9705/AD9706/AD9707 1.0 0.5 0 –0.5 –1.0 –1.5 0 5000 10000 CODE Figure 19. Typical Uncalibrated INL 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 0 5000 10000 CODE Figure 20. Typical Uncalibrated DNL 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 5000 10000 CODE Figure 21. Typical Calibrated INL 0.6 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 0 15000 +25°C ...
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... FREQUENCY (MHz) Figure 25. Dual-Tone SFDR f = 78MSPS CLOCK f = 15.0MHz OUT1 f = 15.4MHz OUT2 SFDR = 77dBc AMPLITUDE = 0dBFS –100 –110 Rev Page AD9704/AD9705/AD9706/AD9707 –10 f CLOCK –20 f OUT1 f OUT2 –30 f OUT3 f OUT4 –40 SFDR = 77dBc AMPLITUDE = 0dBFS –50 –60 –70 –80 –90 ...
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... AD9704/AD9705/AD9706/AD9707 VDD = 1 mA, unless otherwise noted. OUTFS 95 10MSPS 90 65MSPS 80MSPS FREQUENCY (MHz) Figure 27. SFDR vs (MHz) OUT Figure 28. SFDR vs MSPS OUT ...
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... Figure 36. Dual-Tone IMD vs. Lower f OUTFS 125MSPS and 0 dBFS Figure 37. Dual-Tone IMD vs. Lower f OUTFS 125MSPS and 0 dBFS OUTFS Rev Page AD9704/AD9705/AD9706/AD9707 –40°C 75 +85° +25° ...
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... AD9704/AD9705/AD9706/AD9707 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 0 5000 10000 CODE Figure 39. Typical Uncalibrated DNL –40° +85°C +25° (MHz) OUT Figure 40. SFDR vs. Temperature at 80 MSPS –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 – ...
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... OUTFS –115 –120 –125 –130 –135 –140 12-BIT –145 14-BIT –150 –155 –160 (MHz) OUT Figure 44. AD9704, AD9705, AD9706, AD9707 NSD vs. f 175 MSPS 0.03 0.02 0.01 0 –0.01 –0. 100 150 CODE Figure 45. AD9704 Typical Uncalibrated INL 0.01 0 –0.01 –0.02 –0.03 0 ...
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... SFDR = 67dBc AMPLITUDE = 0dBFS –40 –50 –60 –70 –80 –90 –100 –110 FREQUENCY (MHz) Figure 52. AD9704 Dual-Tone SFDR 3000 4000 = 78MSPS CLOCK = 15.0MHz OUT 78MSPS CLOCK = 15.0MHz OUT1 = 15.4MHz OUT2 Rev Page –10 ...
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... Data Sheet –10 f – –30 SFDR = 77dBc AMPLITUDE = 0dBFS –40 –50 –60 –70 –80 –90 –100 –110 FREQUENCY (MHz) Figure 56. AD9706 Dual-Tone SFDR = 78MSPS CLOCK = 15.0MHz OUT1 = 15.4MHz OUT2 Rev Page AD9704/AD9705/AD9706/AD9707 ...
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... OUT Figure 57. AD9704, AD9705, AD9706, AD9707 NSD vs. f 0.04 0.03 0.02 0.01 0 –0.01 –0. 100 150 CODE Figure 58. AD9704 Typical Uncalibrated INL 0.01 0 –0.01 –0.02 –0. 100 ...
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... SFDR = 67dBc –30 AMPLITUDE = 0dBFS –40 –50 –60 –70 –80 –90 –100 –110 FREQUENCY (MHz) Figure 64. AD9704 Single-Tone SFDR –10 f – –30 SFDR = 67dBc AMPLITUDE = 0dBFS –40 –50 –60 –70 –80 –90 –100 –110 ...
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... AD9704/AD9705/AD9706/AD9707 –10 f – –30 SFDR = 73dBc AMPLITUDE = 0dBFS –40 –50 –60 –70 –80 –90 –100 –110 FREQUENCY (MHz) Figure 69. AD9706 Dual-Tone SFDR = 78MSPS CLOCK = 15.0MHz OUT1 = 15.4MHz OUT2 Rev Page Data Sheet ...
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... CLKVDD CLKCOM SEGMENTED LSB SWITCHES SWITCHES AD9512 CLK+ CLK1 LATCHES CLK– CLKB DVDD DCOM DIGITAL DATA CLOCK OUTPUT DIGITAL DATA SOURCE DPG Figure 70. Basic AC Characterization Test Setup Rev Page AD9704/AD9705/AD9706/AD9707 ACOM AD9707 ADT4-6T+ OTCM IOUTA IOUTB 1kΩ SPI SLEEP/CSB ...
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... AD9707 are referenced to ACOM. General Operation of the Serial Interface There are two phases to a communication cycle with the AD9704/ AD9705/AD9706/AD9707. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9704/AD9705/ AD9706/AD9707, coincident with the first eight SCLK rising edges ...
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... If the SPI port is in the midst of an instruction cycle or a data transfer cycle, none of the present data is written. The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9704/ AD9705/AD9706/AD9707 and the system controller. Phase 2 of the communication cycle is a transfer of one, two, three, or four data bytes, as determined by the instruction byte ...
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... AD9704/AD9705/AD9706/AD9707 INSTRUCTION CYCLE DATA TRANSFER CYCLE CSB SCLK R SDIO N Figure 72. Serial Register Interface Timing, MSB First Write INSTRUCTION CYCLE DATA TRANSFER CYCLE CSB SCLK R SDIO N D7 SDO Figure 73. Serial Register Interface Timing, MSB First Read ...
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... Description 0000 Hardware version identifier Default Description 00 Calibration memory 00 = uncalibrated 01 = self-calibration 10 = not used 11 = user input 000 Calibration clock divide ratio from DAC clock rate 000 = divide by 256 001 = divide by 128 … 110 = divide by 4 111 = divide by 2 Rev Page AD9704/AD9705/AD9706/AD9707 ...
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... OUTFS setting I (R SET I OUTFS power dissipation of the AD9704/AD9705/AD9706/ AD9707, which is proportional to I The second benefit relates to the ability to adjust the output over range, which is useful for controlling the transmitted power. Register Setting Register 0x00, Bit (default) ...
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... OUTFS N DAC CODE = 2 − 1, where 10, 12 for the AD9704, AD9705, AD9706, and AD9707, respectively), while IOUTB, the complementary output, provides no current. The current output appearing at IOUTA and IOUTB is a function of both the input ...
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... AD9704/AD9705/AD9706/AD9707 the output common mode to a value other than ACOM via Pin 19 (OTCM). This extends the compliance range of the outputs and facilitates interfacing the output of the AD9704/AD9705/AD9706/ AD9707 to components that require common-mode levels other than 0 V. The OTCM pin demands dynamically changing current and should be driven by a low source impedance to prevent a common-mode signal from appearing on the DAC outputs ...
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... Data Sheet POWER DISSIPATION The power dissipation the AD9704/AD9705/AD9706/ D AD9707 is dependent on several factors that include • The power supply voltages (AVDD, CLKVDD, and DVDD) • The full-scale current output, I OUTFS • The update rate, f CLOCK • The reconstructed digital input waveform ...
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... Turn off output current and internal band gap reference SELF-CALIBRATION The AD9704/AD9705/AD9706/AD9707 feature that improves the DNL of the device. Performing a self- calibration on the device improves device performance in low frequency applications. The device performance in applications where the analog output frequencies are above 1 MHz are generally ...
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... Wait at least 160 CLK+/CLK− clock cycles 6. Repeat Step 3 through Step 5 for each of the remaining 32 coefficients by incrementing the address by one for each write. 7. Clear the SMEMWR bit by writing 0x00 to Register 0x0F. 8. Disable the calibration clock by clearing the CALCLK bit (Register 0x02, Bit 0). Rev Page AD9704/AD9705/AD9706/AD9707 ...
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... AD9704/AD9705/AD9706/AD9707 APPLICATIONS INFORMATION OUTPUT CONFIGURATIONS The following sections illustrate some typical output configurations for the AD9704/AD9705/AD9706/AD9707. Unless otherwise noted assumed that I nominal 2 mA. For applications requiring the optimum dynamic performance, a differential output configuration is suggested. A differential output configuration can consist of either an RF transformer or a differential op amp configuration. ...
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... The DPG generates Analog Devices provided and user created digital vectors that are input into the AD9704/AD9705/AD9706/AD9707 provided with the evaluation board allows the user to program the registers in the product and the DPG. The AD9704/AD9705/ AD9706/AD9707 port that also provides the SPI port interface. ...
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... SEATING PLANE ORDERING GUIDE Model 1 Temperature Range AD9704BCPZ −40°C to +85°C AD9704BCPZRL7 −40°C to +85°C AD9704-DPG2-EBZ AD9705BCPZ −40°C to +85°C AD9705BCPZRL7 −40°C to +85°C AD9705-DPG2-EBZ AD9706BCPZ −40°C to +85°C AD9706BCPZRL7 −40°C to +85°C AD9706-DPG2-EBZ AD9707BCPZ − ...
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... Data Sheet NOTES AD9704/AD9705/AD9706/AD9707 Rev Page ...
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... AD9704/AD9705/AD9706/AD9707 NOTES ©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05926-0-10/11(B) Rev Page Data Sheet ...