AD9706 Analog Devices, AD9706 Datasheet - Page 39

• Manufacturer Part Number: AD9706
• Manufacturer: Analog Devices

Specifications of AD9706

• Resolution (bits): 12bit
• Dac Update Rate: 175MSPS
• Dac Settling Time: 11ns
• Max Pos Supply (v): +3.6V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Par

Data Sheet
The
and writing of the calibration coefficients. There are 33 coefficients
in total. The read/write feature of the coefficients can be useful
for improving the results of the self-calibration routine by averaging
the results of several calibration results and loading the averaged
results back into the device. The reading and writing routines
follow.
To read the calibration coefficients to the device:
1.
2.
3.
4.
5.
6.
7.
8.
AD9704/AD9705/AD9706/AD9707
Enable the calibration clock by setting the CALCLK bit
(Register 0x02, Bit 0).
Write the address of the first coefficient (0x00) to
Register 0x10.
Set the SMEMRD bit (Register 0x0F, Bit 2) by writing 0x04
to Register 0x0F.
Wait at least 160 CLK+/CLK− clock cycles.
Read the value of the first coefficient by reading the
contents of Register 0x11.
Clear the SMEMRD bit by writing 0x00 to Register 0x0F.
Repeat Step 2 through Step 6 for each of the remaining 32
coefficients by incrementing the address by one for each
read.
Disable the calibration clock by clearing the CALCLK Bit
(Register 0x02, Bit 0).
devices allow reading
Rev. B | Page 39 of 44
To write the calibration coefficients to the device:
1.
2.
3.
4.
5.
6.
7.
8.
Enable the calibration clock by setting the CALCLK bit
(Register 0x02, Bit 0).
Set the SMEMWR bit (Register 0x0F, Bit 3) by writing 0x08
to Register 0x0F.
Write the address of the first coefficient (0x00) to
Register 0x10.
Write the value of the first coefficient to Register 0x11.
Wait at least 160 CLK+/CLK− clock cycles
Repeat Step 3 through Step 5 for each of the remaining 32
coefficients by incrementing the address by one for each write.
Clear the SMEMWR bit by writing 0x00 to Register 0x0F.
Disable the calibration clock by clearing the CALCLK bit
(Register 0x02, Bit 0).
AD9704/AD9705/AD9706/AD9707