AD5611 Analog Devices, AD5611 Datasheet

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AD5611

Manufacturer Part Number
AD5611
Description
2.7 V to 5.5 V,
Manufacturer
Analog Devices
Datasheet

Specifications of AD5611

Resolution (bits)
10bit
Dac Update Rate
1.7MSPS
Dac Settling Time
6µs
Max Pos Supply (v)
+5.5V
Single-supply
Yes
Dac Type
Voltage Out
Dac Input Format
Ser,SPI

Available stocks

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Part Number:
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Data Sheet
FEATURES
6-lead SC70 and LFCSP packages
Micropower operation: 100 µA maximum at 5 V
Power-down typically to 0.2 µA at 3 V
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to 0 V with brownout detection
3 power-down functions
Low power serial interface with Schmitt-triggered inputs
On-chip output buffer amplifier, rail-to-rail operation
SYNC interrupt facility
Minimized zero-code error
AD5601 buffered 8-bit DAC
AD5611 buffered 10-bit DAC
AD5621 buffered 12-bit DAC
APPLICATIONS
Voltage level setting
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5601/AD5611/AD5621, members of the nanoDAC®
family, are single, 8-/10-/12-bit, buffered voltage output DACs
that operate from a single 2.7 V to 5.5 V supply, consuming
typically 75 µA at 5 V. The parts come in tiny LFCSP and SC70
packages. Their on-chip precision output amplifier allows rail-
to-rail output swing to be achieved. The AD5601/AD5611/
AD5621 utilize a versatile 3-wire serial interface that operates at
clock rates up to 30 MHz and is compatible with SPI, QSPI™,
MICROWIRE™, and DSP interface standards.
The reference for the AD5601/AD5611/AD5621 is derived
from the power supply inputs and, therefore, gives the widest
dynamic output range. The parts incorporate a power-on reset
circuit, which ensures that the DAC output powers up to 0 V
and remains there until a valid write to the device takes place.
The AD5601/AD5611/AD5621 contain a power-down feature
that reduces current consumption to typically 0.2 µA at 3 V.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
B version: ±0.5 LSB INL
B version: ±0.5 LSB INL
A version: ±4 LSB INL
B version: ±1 LSB INL
A version: ±6 LSB INL
nanoDAC, SPI Interface in LFCSP and SC70
2.7 V to 5.5 V, <100 μA, 8-/10-/12-Bit
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
Table 1. Related Devices
Part Number
AD5641
They also provide software-selectable output loads while in
power-down mode. The parts are put into power-down mode
over the serial interface.
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equip-
ment. The combination of small package and low power makes
these nanoDAC devices ideal for level-setting requirements,
such as generating bias or control voltages in space-constrained
and power-sensitive applications.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
SYNC
Available in 6-lead LFCSP and SC70 packages.
Low power, single-supply operation. The AD5601/
AD5611/AD5621 operate from a single 2.7 V to 5.5 V
supply with a maximum current consumption of 100 µA,
making them ideal for battery-powered applications.
The on-chip output buffer amplifier allows the output of
the DAC to swing rail-to-rail with a typical slew rate of
0.5 V/µs.
Reference is derived from the power supply.
High speed serial interface with clock speeds up to
30 MHz. Designed for very low power consumption.
The interface powers up only during a write cycle.
Power-down capability. When powered down, the DAC
typically consumes 0.2 µA at 3 V. Power-on reset with
brownout detection.
CONTROL
POWER-ON
LOGIC
REGISTER
INPUT
SCLK SDIN
RESET
DAC
AD5601/AD5611/AD5621
FUNCTIONAL BLOCK DIAGRAM
Description
2.7 V to 5.5 V, <100 µA, 14-bit nanoDAC in
SC70 and LFCSP packages
©2005–2012 Analog Devices, Inc. All rights reserved.
REF(+)
12-/10-/8-BIT
V
DD
DAC
CONTROL LOGIC
POWER-DOWN
GND
Figure 1.
AD5601/AD5611/AD5621
OUTPUT
BUFFER
www.analog.com
RESISTOR
NETWORK
V
OUT

Related parts for AD5611

AD5611 Summary of contents

Page 1

... PRODUCT HIGHLIGHTS 1. Available in 6-lead LFCSP and SC70 packages. 2. Low power, single-supply operation. The AD5601/ AD5611/AD5621 operate from a single 2 5.5 V supply with a maximum current consumption of 100 µA, making them ideal for battery-powered applications. 3. The on-chip output buffer amplifier allows the output of the DAC to swing rail-to-rail with a typical slew rate of 0.5 V/µ ...

Page 2

... SYNC Interrupt .......................................................................... 14 Power-On Reset .......................................................................... 16 Power-Down Modes .................................................................. 16 Microprocessor Interfacing ....................................................... 16 Applications ..................................................................................... 18 Choosing a Reference as Power Supply for the AD5601/AD5611/AD5621 ....................................................... 18 Bipolar Operation Using the AD5601/AD5611/AD5621 ..... 18 Using the AD5601/AD5611/AD5621 with a Galvanically Isolated Interface ........................................................................ 19 Power Supply Bypassing and Grounding ................................ 19 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 21 12/07—Rev Rev. C Changes to Features .......................................................................... 1 Changes to Table 2 ...

Page 3

... Rev Page AD5601/AD5611/AD5621 unless otherwise noted. Temperature range MAX Max Unit Test Conditions/Comments Bits ±0.5 LSB ±0.5 LSB Guaranteed monotonic by design Bits ±0.5 LSB ±0.5 LSB Guaranteed monotonic by design Bits ±1 LSB ± ...

Page 4

... I /I OUT DD 1 Linearity calculated using a reduced code range: AD5621 from Code 64 to Code 4032; AD5611 from Code 16 to Code 1008; AD5601 from Code 4 to Code 252. 2 Guaranteed by design and characterization, not production tested. 3 Total current flowing into all pins. TIMING CHARACTERISTICS 5.5 V ...

Page 5

... 0 maximum rating conditions for extended periods may affect −0 0 device reliability. −40°C to +125°C −65°C to +160°C ESD CAUTION 150°C 433.34°C/W 149.47°C/W 95°C/W 215°C 220°C 2.0 kV Rev Page AD5601/AD5611/AD5621 ...

Page 6

... SDIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input Power Supply Input. The AD5601/AD5611/AD5621 can be operated from 2 5 decoupled to GND GND Ground. Ground reference point for all circuitry on the AD5601/AD5611/AD5621. ...

Page 7

... REF T = 25° 116 216 316 416 516 616 716 816 DAC CODE Figure 9. AD5611 Total Unadjusted Error (TUE REF T = 25° 104 154 DAC CODE Figure 10. AD5601 Total Unadjusted Error (TUE) 3564 4064 ...

Page 8

... DAC CODE Figure 11. Typical AD5621 DNL 25° 116 216 316 416 516 616 DAC CODE Figure 12. Typical AD5611 DNL 0.010 0.008 T = 25°C A 0.006 0.004 0.002 0 –0.002 –0.004 –0.006 –0.008 –0.010 ...

Page 9

... V = 70mV OUT 25° 25° 400 500 Rev Page AD5601/AD5611/AD5621 25°C A MIDSCALE LOADED CH1 CH1 5µV/DIV Figure 20. 1/f Noise, 0 Bandwidth CH1 V OUT CH2 CH1 5V, CH2 1V, TIME BASE = 2µs/DIV Figure 21. Exiting Power-Down Mode ...

Page 10

... DD 0.06 AD5621 MAX DNL ERROR 0.05 0.04 0.03 AD5611 MAX DNL ERROR 0.02 0.01 0 –0.01 –0.02 AD5601 MAX DNL ERROR AD5611 MIN DNL ERROR AD5601 MIN DNL ERROR –0.03 –0.04 –0.05 –0.06 AD5621 MIN DNL ERROR –0.07 –0.08 – 110 TEMPERATURE (°C) Figure 27. DNL vs. Temperature (5 V) ...

Page 11

... SUPPLY VOLTAGE (V) Figure 33. INL vs. Supply Voltage at 25°C 0.10 0.09 0.08 0.07 0.06 0.05 0.04 AD5621 MAX DNL ERROR 0.03 0.02 AD5611 MAX DNL ERROR 0.01 0 AD5611 MIN DNL ERROR AD5601 MAX DNL ERROR AD5601 MIN DNL ERROR AD5621 MIN DNL ERROR 2.7 3.2 3.7 4.2 4.7 5.2 5.7 SUPPLY VOLTAGE (V) Figure 34. DNL vs. Supply Voltage at 25°C 100 ...

Page 12

... A AD5621 ZERO-CODE ERROR 0.0008 0.0006 0.0004 AD5601 FULL-SCALE ERROR AD5611 ZERO-CODE ERROR 0.0002 AD5601 ZERO-CODE ERROR 0 AD5611 FULL-SCALE ERROR –0.0002 AD5621 FULL-SCALE ERROR –0.0004 2.7 3.2 3.7 4.2 4.7 SUPPLY VOLTAGE (V) Figure 36. Zero-Code Error and Full-Scale Error vs. Supply Voltage at 25°C AD5621 MAX TUE 4 ...

Page 13

... DAC register. Ideally, the output should The zero-code error is always positive in the AD5601/AD5611/AD5621 because the output of the DAC cannot go below 0 V. Zero-code error is due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is expressed in mV ...

Page 14

... AD5621. See Figure 42 and TO OUTPUT AMPLIFIER Figure 43 for the AD5611 and AD5601 input shift register map. SYNC INTERRUPT In a normal write sequence, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the falling edge ...

Page 15

... Figure 41. AD5621 Input Register Contents DATA BITS 0 NORMAL OPERATION 1kΩ TO GND 1 POWER-DOWN MODES 100kΩ TO GND 0 1 THREE-STATE Figure 42. AD5611 Input Register Contents DB0 (LSB DATA BITS 0 NORMAL OPERATION 1kΩ TO GND 1 POWER-DOWN MODES 100kΩ TO GND 0 1 THREE-STATE Figure 43 ...

Page 16

... SPORT is enabled. *ADDITIONAL PINS OMITTED FOR CLARITY Figure 46. AD5601/AD5611/AD5621 to AD5601/AD5611/AD5621 to 68HC11/68L11 Interface Figure 47 shows a serial interface between the AD5601/AD5611/ AD5621 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK of the AD5601/AD5611/ AD5621, while the MOSI output drives the serial data line of the DAC ...

Page 17

... SPORT1 and SPORT0, for serial and multiprocessor communications. Using SPORT0 to connect to the AD5601/AD5611/AD5621, the setup for the interface is as follows: DT0PRI drives the SDIN pin of the AD5601/AD5611/ AD5621, while TSCLK0 drives the SCLK of the part. The SYNC is driven from TFS0. ...

Page 18

... ADR395 SYNC 3-WIRE AD5601/AD5611/ SERIAL SCLK AD5621 INTERFACE SDIN Figure 51. ADR395 as Power Supply to the AD5601/AD5611/AD5621 Some recommended precision references for use as supplies to the AD5601/AD5611/AD5621 are listed in Table 7. Table 7. Precision References for the AD5601/AD5611/AD5621 Initial Accuracy Temp Drift Part No. (mV max) (ppm/°C max) ADR435 ± ...

Page 19

... The PCB containing the AD5601/AD5611/AD5621 should have separate analog and digital sections, each having its own area of the board. If the AD5601/AD5611/AD5621 are in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. ...

Page 20

... AD5601/AD5611/AD5621 OUTLINE DIMENSIONS 1.00 0.90 0.70 0.10 MAX COPLANARITY 0.10 PIN 1 INDEX AREA 0.80 0.75 0.70 SEATING PLANE 2.20 2.00 1.80 2.40 1. 2.10 1.25 1.80 1. 0.65 BSC 1.30 BSC 0.40 1.10 0.10 0.80 0.22 SEATING 0.30 0.08 PLANE 0.15 COMPLIANT TO JEDEC STANDARDS MO-203-AB Figure 54. 6-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-6) Dimensions shown in millimeters 1.50 1.40 2.10 1.30 2.00 1.90 4 3.10 EXPOSED PAD 3.00 2.90 0.45 0.40 0.35 3 TOP VIEW BOTTOM VIEW FOR PROPER CONNECTION OF ...

Page 21

... AD5611AKSZ-500RL7 –40°C to +125°C AD5611AKSZ-REEL7 –40°C to +125°C AD5611ACPZ-RL7 –40°C to +125°C AD5611BKSZ-500RL7 –40°C to +125°C AD5611BKSZ-REEL7 –40°C to +125°C AD5621AKSZ-500RL7 –40°C to +125°C AD5621AKSZ-REEL7 –40°C to +125°C AD5621ACPZ-RL7 –40°C to +125°C AD5621BKSZ-500RL7 – ...

Page 22

... AD5601/AD5611/AD5621 NOTES Rev Page Data Sheet ...

Page 23

... Data Sheet NOTES AD5601/AD5611/AD5621 Rev Page ...

Page 24

... AD5601/AD5611/AD5621 NOTES ©2005–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06853-0-2/12(F) Rev Page Data Sheet ...

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