AD5621 Analog Devices, AD5621 Datasheet
AD5621
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AD5621 Summary of contents
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... PRODUCT HIGHLIGHTS 1. Available in 6-lead LFCSP and SC70 packages. 2. Low power, single-supply operation. The AD5601/ AD5611/AD5621 operate from a single 2 5.5 V supply with a maximum current consumption of 100 µA, making them ideal for battery-powered applications. 3. The on-chip output buffer amplifier allows the output of the DAC to swing rail-to-rail with a typical slew rate of 0.5 V/µ ...
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... SYNC Interrupt .......................................................................... 14 Power-On Reset .......................................................................... 16 Power-Down Modes .................................................................. 16 Microprocessor Interfacing ....................................................... 16 Applications ..................................................................................... 18 Choosing a Reference as Power Supply for the AD5601/AD5611/AD5621 ....................................................... 18 Bipolar Operation Using the AD5601/AD5611/AD5621 ..... 18 Using the AD5601/AD5611/AD5621 with a Galvanically Isolated Interface ........................................................................ 19 Power Supply Bypassing and Grounding ................................ 19 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 21 12/07—Rev Rev. C Changes to Features .......................................................................... 1 Changes to Table 2 ...
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... Rev Page AD5601/AD5611/AD5621 unless otherwise noted. Temperature range MAX Max Unit Test Conditions/Comments Bits ±0.5 LSB ±0.5 LSB Guaranteed monotonic by design Bits ±0.5 LSB ±0.5 LSB Guaranteed monotonic by design Bits ±1 LSB ± ...
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... I /I OUT DD 1 Linearity calculated using a reduced code range: AD5621 from Code 64 to Code 4032; AD5611 from Code 16 to Code 1008; AD5601 from Code 4 to Code 252. 2 Guaranteed by design and characterization, not production tested. 3 Total current flowing into all pins. TIMING CHARACTERISTICS 5.5 V ...
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... 0 maximum rating conditions for extended periods may affect −0 0 device reliability. −40°C to +125°C −65°C to +160°C ESD CAUTION 150°C 433.34°C/W 149.47°C/W 95°C/W 215°C 220°C 2.0 kV Rev Page AD5601/AD5611/AD5621 ...
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... SDIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input Power Supply Input. The AD5601/AD5611/AD5621 can be operated from 2 5 decoupled to GND GND Ground. Ground reference point for all circuitry on the AD5601/AD5611/AD5621. ...
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... Rev Page AD5601/AD5611/AD5621 REF T = 25° 564 1064 1564 2064 2564 3064 DAC CODE Figure 8. AD5621 Total Unadjusted Error (TUE REF T = 25° 116 216 316 416 516 616 716 816 DAC CODE Figure 9 ...
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... AD5601/AD5611/AD5621 0. 25°C A 0.15 0.10 0. –0.05 –0.10 –0.15 –0.20 64 564 1064 1564 2064 DAC CODE Figure 11. Typical AD5621 DNL 25° 116 216 316 416 516 616 DAC CODE Figure 12. Typical AD5611 DNL 0.010 0.008 T = 25°C A 0.006 ...
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... V = 70mV OUT 25° 25° 400 500 Rev Page AD5601/AD5611/AD5621 25°C A MIDSCALE LOADED CH1 CH1 5µV/DIV Figure 20. 1/f Noise, 0 Bandwidth CH1 V OUT CH2 CH1 5V, CH2 1V, TIME BASE = 2µs/DIV Figure 21. Exiting Power-Down Mode ...
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... AD5611 MAX DNL ERROR 0.02 0.01 0 –0.01 –0.02 AD5601 MAX DNL ERROR AD5611 MIN DNL ERROR AD5601 MIN DNL ERROR –0.03 –0.04 –0.05 –0.06 AD5621 MIN DNL ERROR –0.07 –0.08 – 110 TEMPERATURE (°C) Figure 27. DNL vs. Temperature ( AD5621 ZERO-CODE ERROR ...
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... AD5621 MIN INL ERROR –0.6 2.7 3.2 3.7 4.2 4.7 SUPPLY VOLTAGE (V) Figure 33. INL vs. Supply Voltage at 25°C 0.10 0.09 0.08 0.07 0.06 0.05 0.04 AD5621 MAX DNL ERROR 0.03 0.02 AD5611 MAX DNL ERROR 0.01 0 AD5611 MIN DNL ERROR AD5601 MAX DNL ERROR AD5601 MIN DNL ERROR AD5621 MIN DNL ERROR 2.7 3.2 3.7 4.2 4.7 5.2 5.7 SUPPLY VOLTAGE (V) Figure 34. DNL vs. Supply Voltage at 25° ...
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... AD5601 FULL-SCALE ERROR AD5611 ZERO-CODE ERROR 0.0002 AD5601 ZERO-CODE ERROR 0 AD5611 FULL-SCALE ERROR –0.0002 AD5621 FULL-SCALE ERROR –0.0004 2.7 3.2 3.7 4.2 4.7 SUPPLY VOLTAGE (V) Figure 36. Zero-Code Error and Full-Scale Error vs. Supply Voltage at 25°C AD5621 MAX TUE 4.7 5.2 5.2 5.7 6.2 6.7 Rev Page 0. 25°C A 0.09 0.08 0.07 0.06 0.05 ...
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... DAC register. Ideally, the output should The zero-code error is always positive in the AD5601/AD5611/AD5621 because the output of the DAC cannot go below 0 V. Zero-code error is due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is expressed in mV ...
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... Power-Down Modes section. For the AD5621, the next 12 bits are the data bits, which are transferred to the DAC register on the 16 the last two bits is ignored by the AD5621. See Figure 42 and TO OUTPUT AMPLIFIER Figure 43 for the AD5611 and AD5601 input shift register map. ...
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... FALLING EDGE D10 DATA BITS 0 NORMAL OPERATION 1kΩ TO GND 1 POWER-DOWN MODES 100kΩ TO GND 0 1 THREE-STATE Figure 41. AD5621 Input Register Contents DATA BITS 0 NORMAL OPERATION 1kΩ TO GND 1 POWER-DOWN MODES 100kΩ TO GND 0 1 THREE-STATE Figure 42. AD5611 Input Register Contents ...
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... Data is transmitted MSB first. To load data to the AD5601/AD5611/ AD5621, PC7 is left low after the first eight bits are transferred and a second serial write operation is performed to the DAC. PC7 is taken high at the end of this procedure. ...
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... SPORT1 and SPORT0, for serial and multiprocessor communications. Using SPORT0 to connect to the AD5601/AD5611/AD5621, the setup for the interface is as follows: DT0PRI drives the SDIN pin of the AD5601/AD5611/ AD5621, while TSCLK0 drives the SCLK of the part. The SYNC is driven from TFS0. ADSP-BF53x* DT0PRI ...
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... R-8 package) and provides very good noise performance at 3.4 µV p-p in the 0 range. Because the supply current required by the AD5601/AD5611/ AD5621 is extremely low, the parts are ideal for low supply applications. The ADR395 voltage reference is recommended in this case. It requires less than 100 µ ...
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... The PCB containing the AD5601/AD5611/AD5621 should have separate analog and digital sections, each having its own area of the board. If the AD5601/AD5611/AD5621 are in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. ...
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... AD5601/AD5611/AD5621 OUTLINE DIMENSIONS 1.00 0.90 0.70 0.10 MAX COPLANARITY 0.10 PIN 1 INDEX AREA 0.80 0.75 0.70 SEATING PLANE 2.20 2.00 1.80 2.40 1. 2.10 1.25 1.80 1. 0.65 BSC 1.30 BSC 0.40 1.10 0.10 0.80 0.22 SEATING 0.30 0.08 PLANE 0.15 COMPLIANT TO JEDEC STANDARDS MO-203-AB Figure 54. 6-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-6) Dimensions shown in millimeters 1.50 1.40 2.10 1.30 2.00 1.90 4 3.10 EXPOSED PAD 3.00 2.90 0.45 0.40 0.35 3 TOP VIEW BOTTOM VIEW FOR PROPER CONNECTION OF ...
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... AD5621AKSZ-REEL7 –40°C to +125°C AD5621ACPZ-RL7 –40°C to +125°C AD5621BKSZ-500RL7 –40°C to +125°C AD5621BKSZ-REEL7 –40°C to +125°C EVAL-AD5621EBZ RoHS Compliant Part. INL Package Description ±0.5 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] ±0.5 LSB 6-Lead Thin Shrink Small Outline Transistor Package [SC70] ± ...
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... AD5601/AD5611/AD5621 NOTES Rev Page Data Sheet ...
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... Data Sheet NOTES AD5601/AD5611/AD5621 Rev Page ...
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... AD5601/AD5611/AD5621 NOTES ©2005–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06853-0-2/12(F) Rev Page Data Sheet ...