AD5641 Analog Devices, AD5641 Datasheet - Page 6

• Manufacturer Part Number: AD5641
• Description: 2.7 V to 5.5 V,
• Manufacturer: Analog Devices

Specifications of AD5641

• Resolution (bits): 14bit
• Dac Update Rate: 1.7MSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AD5641
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
SC70
Pin No.
1
2
3
4
5
6
LFCSP
Pin No.
4
2
3
1
5
6
Figure 3. 6-Lead SC70 Pin Configuration
SYNC
SCLK
SDIN
1
2
3
Mnemonic
SYNC
SCLK
SDIN
V
GND
V
EP
DD
OUT
(Not to Scale)
AD5641
TOP VIEW
6
5
4
Description
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input
data. When SYNC goes low, it enables the input shift register and data is transferred in on the falling
edges of the clocks that follow. The DAC is updated following the 16
taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write
sequence is ignored by the DAC.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates up to 30 MHz.
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
Power Supply Input. The AD5641 can be operated from 2.7 V to 5.5 V. V
GND.
Ground Reference Point for All Circuitry on the AD5641.
Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.
Exposed Pad. Connect to GND.
V
GND
V
OUT
DD
Rev. D | Page 6 of 20
SCLK
NOTES:
1. CONNECT THE EXPOSED PAD TO GND.
Figure 4. 6-Lead LFCSP Pin Configuration
SDIN
V
DD
1
2
3
(Not to Scale)
AD5641
TOP VIEW
th
clock cycle unless SYNC is
DD
should be decoupled to
6 V
5 GND
4 SYNC
OUT
Data Sheet