AD5546 Analog Devices, AD5546 Datasheet - Page 11

• Manufacturer Part Number: AD5546
• Description: Current-Output Parallel-Input, 16-Bit Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD5546

• Resolution (bits): 16bit
• Dac Update Rate: 2MSPS
• Dac Settling Time: 500ns
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Par

Data Sheet
DIGITAL SECTION
The AD5546/AD5556 have 16-/14-bit parallel inputs. The devices are double buffered with 16-/14-bit registers. The double-buffered
feature allows the update of several AD5546/AD5556 simultaneously. For the AD5546, the input register is loaded directly from a 16-bit
controller bus when the WR pin is brought low. The DAC register is updated with data from the input register when LDAC is brought
high. Updating the DAC register updates the DAC output with the new data (see Figure 17). To make both registers transparent, tie WR
low and LDAC high. The asynchronous RS pin resets the part to zero scale if the MSB pin = 0 and to midscale if the MSB pin = 1.
Table 5. AD5546 Parallel Input Data Format
Bit Position
Data Word
Table 6. AD5556 Parallel Input Data Format
Bit Position
Data Word
Table 7. Control Inputs
RS
0
1
1
1
1
1
1
ESD PROTECTION CIRCUITS
All logic input pins contain back-biased ESD protection Zeners
connected to ground (GND) and V
a result, the voltage level of the logic input should not be greater
than the supply voltage.
AMPLIFIER SELECTION
In addition to offset voltage, the bias current is important in op
amp selection for precision current output DACs. An input bias
current of 30 nA in the op amp contributes to 1 LSB in the
AD5546’s full-scale error. The OP1177 and AD8628 op amps
X = don’t care.
WR
X
0
1
0
1
1
LDAC
X
0
1
1
0
Figure 18. Equivalent ESD Protection Circuits
1
MSB
B15
D15
MSB
B13
D13
V
DD
DIGITAL
INPUTS
Register Operation
Reset output to 0, with MSB pin = 0 and to midscale with MSB pin = 1.
Load input register with data bits.
Load DAC register with the contents of the input register.
Input and DAC registers are transparent.
When LDAC and WR are tied together and programmed as a pulse, the data bits are loaded into the input register on
the falling edge of the pulse and then loaded into the DAC register on the rising edge of the pulse.
No register operation.
B14
D14
B12
D12
5kΩ
DGND
B13
D13
DD
B11
D11
, as shown in Figure 18. As
B12
D12
B10
D10
B11
D11
B9
D9
B10
D10
Rev. D | Page 11 of 20
B8
D8
B9
D9
B7
D7
B8
D8
are good candidates for the I-V conversion.
REFERENCE SELECTION
The initial accuracy and the rated output of the voltage refer-
ence determine the full span adjustment. The initial accuracy is
usually a secondary concern in precision because it can be
trimmed. Figure 23 shows an example of a trimming circuit.
The zero scale error can also be minimized by standard op amp
nulling techniques.
The voltage reference temperature coefficient (TC) and long-
term drift are primary considerations. For example, a 5 V ref-
erence with a TC of 5 ppm/
25 µV per degree Celsius. As a result, the reference that operates
at 55
Similarly, the same 5 V reference with a ±50 ppm long-term
drift means that the output may change by ±250 µV over time.
Therefore, it is practical to calibrate a system periodically to
maintain its optimum precision.
o
C contributes an additional 750 µV full-scale error.
B7
D7
B6
D6
B6
D6
B5
D5
B5
D5
B4
D4
o
C means that the output changes by
B4
D4
B3
D3
B3
D3
AD5546/AD5556
B2
D2
B2
D2
B1
D1
B1
D1
LSB
B0
D0
LSB
B0
D0