AD9775 Analog Devices, AD9775 Datasheet
AD9775
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... One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 Digital-to-Analog Converter IDAC COS GAIN DAC SIN IMAGE REJECTION/ I/Q DAC DUAL DAC GAIN/OFFSET MODE REGISTERS BYPASS MUX SIN COS IDAC ) DIFFERENTIAL CLK ©2006 Analog Devices, Inc. All rights reserved. AD9775 OFFSET DAC I OUT www.analog.com ...
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... Image Rejection and Sideband Suppression of Modulated Carriers ........................................................................................ 38 Applying the Output Configurations........................................... 42 Unbuffered Differential Output, Equivalent Circuit ............. 42 Differential Coupling Using a Transformer............................ 42 Differential Coupling Using an Op Amp................................ 43 Interfacing the AD9775 with the AD8345 Quadrature Modulator.................................................................................... 43 Evaluation Board ............................................................................ 44 Outline Dimensions ....................................................................... 54 Ordering Guide .......................................................................... 54 Rev Page ...
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... Edits to Figure 21 .......................................................................... 25 Edits to PLL Disabled, Two-Port Mode ..................................... 25 Edits to Figure 22 .......................................................................... 25 Edits to Figure 23 .......................................................................... 26 Edits to Figure 26a ........................................................................ 27 Edits to Complex Modulation and Image Rejection of Baseband Signals ............................................................................................. 31 Edits to Evaluation Board ............................................................ 39 Edits to Figures 56–59 .................................................................. 40 Replaced Figures 60–69................................................................ 42 Updated Outline Dimensions...................................................... 49 Rev Page AD9775 ...
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... S S and image rejection when combined with an analog quadrature modulator. In this mode, the AD9775 accepts I and Q complex data (representing a single or multicarrier waveform), generates a quadrature modulated IF signal along with its orthogonal representation via its dual DACs, and presents these two reconstructed orthogonal IF carriers to an analog quadrature modulator to complete the image rejection upconversion process ...
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... FSR −1.0 +1 FSR −1.0 ±0.1 +1 FSR −1.0 +1.25 V 200 kΩ 1.14 1.20 1.26 V 100 nA 0.1 1. kΩ 0.5 MHz 0 ppm of FSR/°C 50 ppm of FSR/°C ±50 ppm/°C 3.1 3.3 3 3.1 3.3 3.5 V 8.5 10.0 mA 23.5 mA 3.1 3.3 3 380 410 mW 1.75 W 6.0 mW ±0 FSR/V −40 +85 °C AD9775 ...
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... MHz) 72 AD9775 Max Unit MSPS pA/√Hz dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBFS dBFS ...
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... Rev Page mA, unless otherwise noted. OUTFS Min Typ Max 2 0.9 −10 +10 −10 + 0.75 1.5 2.25 0.5 1 1.5 2 0.9 −10 +10 −10 +10 5 DRVDD − 0.6 0 AD9775 Unit V V μA μ MHz μA μ ...
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... AD9775 DIGITAL FILTER SPECIFICATIONS Table 4. Half-Band Filter No. 1 (43 Coefficients) Tap Coefficient − −134 244 10 11, 33 −414 12 13, 31 673 14 15, 29 −1079 16 17, 27 1772 18 19, 25 −3280 20, 24 ...
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... JA soldered in a circuit board for surface-mount packages. Table 8. Thermal Resistance Package Type 80-Lead Thin Quad Flat Package (TQFP_EP), Exposed Pad Rev Page AD9775 Rating −0 +4.0 V −4 +4.0 V −0 +0.3 V −0 AVDD + 0.3 V −1 AVDD + 0.3 V −0 DVDD + 0.3 V − ...
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... AD9775 8 TxDAC+ 9 TOP VIEW (Not to Scale Figure 5. Pin Configuration Rev Page AD9775 60 FSADJ1 59 FSADJ2 58 REFIO 57 RESET 56 SPI_CSB 55 SPI_CLK 54 SPI_SDIO SPI_SDO 53 DGND 52 DVDD ...
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... With the PLL disabled and the AD9775 in one-port mode, this pin becomes a clock output that runs at twice the input data rate of the I and Q channels. This allows the AD9775 to accept and demux interleaved I and Q data to the I and Q input registers. Port 2 Data Inputs. ...
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... AD9775 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3 Ω doubly terminated, unless otherwise noted –10 –20 –30 –40 –50 –60 –70 –80 – FREQUENCY (MHz) Figure 6. Single-Tone Spectrum @ MSPS with f DATA 90 0dBFS 85 –6dBFS 80 75 –12dBFS 70 65 ...
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... MSPS Figure 16. Third-Order IMD Products vs 160 MSPS Figure 17. Third-Order IMD Products vs. f Rev Page AD9775 –6dBFS –3dBFS 0dBFS FREQUENCY (MHz MSPS OUT DATA –6dBFS 0dBFS –3dBFS ...
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... AD9775 90 8 × × 2 × × FREQUENCY (MHz) Figure 18. Third-Order IMD Products vs. f OUT 1× 160 MSPS, 2× 160 MSPS, 4× f DATA DATA 8× MSPS DATA 90 4× 2× – ...
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... Rev Page FREQUENCY (MHz) = 150 MSPS, Interpolation = 4× DATA 50 100 150 200 250 FREQUENCY (MHz MHz, OUT MSPS, Interpolation = 4× DATA FREQUENCY (MHz MHz, OUT MSPS, Interpolation = 8× DATA AD9775 50 300 25 ...
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... AD9775 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 100 200 FREQUENCY (MHz) Figure 30. Single-Tone Spurious Performance MSPS, Interpolation = 8× DATA 0 –20 –40 –60 –80 –100 –120 300 400 MHz, OUT Rev Page FREQUENCY (MHz) Figure 31 ...
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... For reference drift, the drift is reported in ppm per °C. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental expressed as a percentage or in decibels (dB). Rev Page AD9775 For MIN MAX ...
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... Bit 7 Bit 6 Bit 5 QDAC Fine Gain Adjustment QDAC Offset QDAC Offset QDAC Offset Adjustment Adjustment Adjustment Bit 7 Bit 6 Bit 5 Rev Page AD9775 Bit 2 Bit 1 Bit 0 1R/2R Mode PLL_LOCK DAC Output Indicator Current Set by One or Two External Resistors −jωt ...
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... FULLSCALE Bit 6: Logic 0 (default) places the AD9775 in two-port mode. , SET I and Q data enters the AD9775 via Ports 1 and 2, respectively. A Logic 1 places the AD9775 in one-port mode in which interleaved I and Q data is applied to Port 1. See Table 9 for detailed information on how to use the DATACLK/PLL_LOCK, IQSEL, and ONEPORTCLK modes. ...
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... AD9775 ADDRESS 0x03 Bit 7: Allows the data rate clock (divided down from the DAC clock output at either the DATACLK/PLL_LOCK pin (Pin the SPI_SDO pin (Pin 53). The default this register enables the data rate clock at DATACLK/ PLL_LOCK, while this register causes the data rate clock to be output at SPI_SDO ...
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... GENERAL OPERATION OF THE SERIAL INTERFACE There are two phases to a communication cycle with the AD9775. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9775 coincident with the first eight SCLK rising edges. The instruction byte provides the ...
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... Transfer 4 Bytes functionality is controlled by the LSB-first bit in Register 0. The default is MSB first. When this bit is set active high, the AD9775 serial port is in LSB-first format. In LSB-first mode, the instruction byte and data bytes must be written from LSB to MSB. In LSB-first mode, the serial port internal byte address generator increments for each byte of the multibyte communication cycle ...
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... Figure 34. Serial Register Interface Timing LSB First t SCLK t t PWH PWL t DH INSTRUCTION BIT 6 Figure 35. Timing Diagram for Register Write to AD9775 t DV DATA BIT N DATA BIT N–1 Figure 36. Timing Diagram for Register Read from AD9775 Rev Page DATA TRANSFER CYCLE D2 D1 ...
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... AD9775 DAC OPERATION The dual, 14-bit DAC output of the AD9775, along with the reference circuitry, gain, and offset registers, is shown in Figure 37. Note that an external reference can be used by simply overdriving the internal reference with the external reference. Referring to the transfer functions in Equation 1, a reference current is set by the internal 1 ...
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... If the AD9775 is dc- coupled to an external modulator, this feature can be used to cancel the output offset on the AD9775 as well as the input offset on the modulator. Figure 42 shows a typical example of the effect that the offset control has on LO suppression. ...
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... AD9775 A transformer, such as the T1-1T from Mini-Circuits®, can also be used to convert a single-ended clock to differential. This method is used on the AD9775 evaluation board so that an external sine wave with no dc offset can be used as a differential clock. PECL/ECL drivers require varying termination networks, the details of which are left out of Figure 43 and Figure 44 but can be found in application notes such as AND8020/D from ON Semiconductor® ...
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... Figure 48. PLL_LOCK Output Signal (Pin 8) in the Process of Locking (Typical Lock Time important to note that the resistor/capacitor needed for the PLL loop filter is internal on the AD9775. This suffices unless the input data rate is below 10 MHz, in which case an external series RC is required between the LPF pin and CLKVDD pins. ...
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... The digital data input ports can be configured as two independ- ent ports single (one-port mode) port. In two-port mode, data at the two input ports is latched into the AD9775 on every rising edge of the data rate clock (DATACLK). Also, in two-port mode, the AD9775 can be programmed to generate an externally available DATACLK for the purpose of data synchronization ...
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... I and Q channels. The selection of the data for the I or the Q channel is determined by the state of the logic level at Pin 31 (IQSEL when the AD9775 is in one-port mode) on the rising edge of ONEPORTCLK. Under these conditions, IQSEL = 0 latches the data into the I channel on the clock rising edge, while IQSEL = 1 latches the data into the Q channel ...
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... DATACLK signal at Pin 8, which runs at the input data rate and can be used to synchronize the input data. Data is latched into input Port 1 and Port 2 of the AD9775 on the rising edge of DATACLK. DATACLK speed is defined as the speed of CLKIN divided by the interpolation rate. With zero stuffing enabled, this division increases by a factor of 2 ...
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... The rate of interpolation is determined by the state of Control Register 0x01, Bit 7 and Bit 6. Figure 2 to Figure 4 show the response of the digital filters when the AD9775 is set to 2×, 4×, and 8× modes. The frequency axes of these graphs are normalized to the input data rate of the DAC. As the graphs show, the digital filters can provide greater than out-of-band rejection ...
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... With Control Register 0x01, Bit 7 and Bit 6 set to 00, the interpolation function on the AD9775 is disabled. Figure 59 through Figure 62 show the DAC output spectral characteristics of the AD9775 in the various modulation modes, all with the interpolation filters disabled. The modulation frequency is determined by the state of Control Register 0x01, Bit 5 and Bit 4. ...
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... MODULATION, INTERPOLATION = 2× With Control Register 0x01, Bit 7 and Bit 6 set to 01, the interpolation rate of the AD9775 is 2×. Modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (+1, −1). Figure 63 through Figure 66 represent the spectral response of the AD9775 DAC output with 2× ...
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... OUT DATA Figure 68. 4× Interpolation, Modulation = f Figure 67 through Figure 70 represent the spectral response of the AD9775 DAC output with 4× interpolation in the various modulation modes to a narrow-band baseband signal. 0 –20 –40 –60 –80 –100 –20 – ...
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... Figure 71 through Figure 74 represent the spectral response of the AD9775 DAC output with 8× interpolation in the various modulation modes to a narrow-band baseband signal. The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation = 8× ...
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... This image may be the desired signal application using one of the various modulation modes in the AD9775. This roll-off of image frequencies can be seen in Figure 59 to Figure 74, where the effect of the interpolation and modulation rate is apparent as well. ...
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... It is important to remember that in this application (two baseband data channels) the image rejection is not dependent on the data at either of the AD9775 input channels. In fact, image rejection still occurs with either one or both of the AD9775 input channels active. Note that by changing the ...
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... Due to this 3 dB increase in signal amplitude, the real and imaginary inputs to the AD9775 must be kept at least 3 dB below full scale when operating with the complex modu- lator. Overranging in the complex modulator results in severe distortion at the DAC output ...
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... AD8345 given the complex input signal to the AD9775 in Figure 89. The data in these graphs was taken with a data rate of 12.5 MSPS at the AD9775 inputs. The interpolation rate of 4× or 8× gives a DAC output data rate of 50 MSPS or 100 MSPS result, ...
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... B C –60 –70 –80 –90 –100 1.0 1.5 2.0 /8 Modulation Figure 89. AD9775 Real DAC Output of Complex Input Signal Near Baseband DAC (Positive Frequencies Only), Interpolation = 4×, No Modulation in AD9775 –10 –20 –30 –40 – –60 –70 –80 –90 –100 2.0 3 ...
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... Now Quadrature Modulated by AD8345 (LO = 800 MHz) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 830 840 850 0 Figure 95. AD9775 Real DAC Output of Complex Input Signal Near Baseband (Positive Frequencies Only), Interpolation = 8×, 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 700 40 50 ...
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... For the typical situation, where I both equal 50 Ω, the equivalent circuit values become V R Note that the output impedance of the AD9775 DAC itself is greater than 100 kΩ and typically has no effect on the impedance of the equivalent output circuit. DIFFERENTIAL COUPLING USING A TRANSFORMER An RF transformer can be used to perform a differential-to- single-ended signal conversion, as shown in Figure 98 ...
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... R necessary if level shifting is required on the op amp output. In Figure 99, AVDD, which is the positive analog supply for both the AD9775 and the op amp, is also used to level shift the differential output of the AD9775 to midsupply, that is, AVDD/2. INTERFACING THE AD9775 WITH THE AD8345 ...
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... PLL enabled and disabled. Refer to Figure 105 to Figure 114, the schematics, and the layout for the AD9775 evaluation board for the jumper locations described in the DAC Single-Ended Outputs section. The AD9775 outputs can be configured for various applications by referring to the following instructions ...
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... TO USE PECL CLOCK DRIVER, SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1. Figure 102. Test Configuration for AD9775 in One-Port Mode with PLL Enabled, Signal Generator Frequency = One-Half Interleaved Input Data Rate, ONEPORTCLK = Interleaved Input Data Rate, DAC Output Data Rate = Signal Generator Frequency × Interpolation Rate ...
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... AND JP39 SHOULD BE SOLDERED. IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 53, JP46 AND JP47 SHOULD BE SOLDERED. SEE THE TWO-PORT DATA INPUT MODE FOR MORE INFORMATION. Figure 103. Test Configuration for AD9775 in Two-Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency, INPUT CLOCK NOTES 1 ...
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... RC0603 G2 ENBL G3 VPS1 VOUT LOIP VPS2 LOIN G4A G1B G4B G1A QBBN IBBN QBBP IBBP ADTL1-12 CC0603 Figure 105. AD8345 Circuitry on AD9775 Evaluation Board Rev Page RC0603 ADTL1-12 CC0805 AD9775 ...
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... AD9775 CC0603 RC0603 CC0603 RC1206 CC0603 RC0603 CC0605 Figure 106. AD9775 Clock, Power Supplies, and Output Circuitry Rev Page CC0805 ...
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... Figure 107. AD9775 Evaluation Board Input (A Channel) and Clock Buffer Circuitry Rev Page AD9775 ...
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... AD9775 Figure 108. AD9775 Evaluation Board Input (B Channel) and SPI Port Circuitry Rev Page ...
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... Figure 109. AD9775 Evaluation Board Components, Top Side Figure 110. AD9775 Evaluation Board Components, Bottom Side Rev Page AD9775 ...
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... AD9775 Figure 112. AD9775 Evaluation Board Layout, Layer Two (Ground Plane) Figure 111. AD9775 Evaluation Board Layout, Layer One (Top) Rev Page ...
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... Figure 113. AD9775 Evaluation Board Layout, Layer Three (Power Plane) Figure 114. AD9775 Evaluation Board Layout, Layer Four (Bottom) Rev Page AD9775 ...
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... MAX PLANE COPLANARITY VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range AD9775BSV −40°C to +85°C AD9775BSVRL −40°C to +85°C 1 AD9775BSVZ −40°C to +85°C 1 AD9775BSVZRL −40°C to +85°C AD9775- Pb-free part. 14.20 14.00 SQ 12.20 13.80 1.20 12.00 SQ MAX 11. PIN 1 TOP VIEW ...
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... NOTES Rev Page AD9775 ...
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... AD9775 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02858-0-12/06(E) Rev Page ...