AD9754 Analog Devices, AD9754 Datasheet
AD9754
Specifications of AD9754
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AD9754 Summary of contents
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... The AD9754 is available in 28-lead SOIC and TSSOP packages specified for operation over the industrial temperature range. PRODUCT HIGHLIGHTS 1. The AD9754 is a member of the wideband TxDAC high per- formance product family that provides an upward or downward component selection path based on resolution ( bits), performance and cost ...
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... AD9754–SPECIFICATIONS DC SPECIFICATIONS ( MIN Parameter RESOLUTION 1 DC ACCURACY Integral Linearity Error (INL + Differential Nonlinearity (DNL + ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) 2 Full-Scale Output Current Output Compliance Range Output Resistance ...
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... Typ Max 2.5 2 –83 –75 –78 – AD9754 Units MSPS pA/ Hz pA/ Hz dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9754 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... DB9 24 AVDD AD9754 DB8 6 23 ICOMP TOP VIEW (Not to Scale DB7 IOUTA DB6 8 21 IOUTB 9 DB5 20 ACOM DB4 DB3 FS ADJ 11 18 DB2 12 17 REFIO DB1 13 16 REFLO 14 15 SLEEP (LSB) DB0 CONNECT PIN FUNCTION DESCRIPTIONS –5– AD9754 ...
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... T . For MIN MAX +5V REFLO AVDD ACOM 150pF AD9754 PMOS CURRENT SOURCE ARRAY LSB SEGMENTED SWITCHES SWITCHES FOR DB13–DB5 LATCHES DIGITAL DATA CLOCK ...
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... MSPS and 0 dBFS OUTFS 85 80 20mA 5mA – – MSPS CLOCK Figure 11. SNR vs MHz and 0 dBFS OUT AD9754 –12dBFS MSPS OUT and OUT 10mA FS 80 100 120 140 and I CLOCK OUTFS ...
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... AD9754 1.0 0.5 0 –0.5 –1.0 –1.5 –2 12k 16k CODE Figure 12. Typical INL 1.0 0.5 0 –0.5 –1 12k 16k CODE Figure 13. Typical DNL 65MSPS CLOCK – 6.25MHz OUT1 f = 6.75MHz OUT2 – 7.25MHz OUT3 f = 7.75MHz –30 OUT4 SFDR > 70dBc AMPLITUDE = 0dBFS –40 –50 – ...
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... FUNCTIONAL DESCRIPTION Figure 16 shows a simplified block diagram of the AD9754. The AD9754 consists of a large PMOS current source array that is capable of providing total current. The array is divided into 31 equal currents that make up the five most significant bits (MSBs). The next four bits or middle bits consist of 15 equal current sources whose value is 1/16th of an MSB current source ...
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... IREF between OUTFS 62.5 A and 625 A. The wide adjustment span of I provides several application benefits. The first benefit relates +5V directly to the power dissipation of the AD9754, which is pro- portional to I AVDD second benefit relates to the 20 dB adjustment, which is useful 150pF for system gain control purposes ...
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... SET –1 set by the breakdown limits of the CMOS process. Operation beyond this maximum limit may result in a break- AVDD down of the output stage and affect the reliability of the AD9754. The positive output compliance range is slightly dependent on AVDD 150pF the full-scale output current, I nominal 1 ...
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... The drivers of the digital data interface circuitry should be specified to meet the minimum setup and hold times of the AD9754 as well as its required min/max input logic level thresholds. Digital signal paths should be kept short and run lengths matched to avoid propagation delay mismatch ...
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... The AD9754 is positive edge triggered, and so exhibits SNR sensitivity when the data transition is close to this edge. In general, the goal when applying the AD9754 is to make the data transitions close to the negative clock edge. This becomes more important as the sample rate increases. Figure 23 shows the relationship of SNR to clock placement ...
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... In this case, AVDD, which is the positive analog supply for both the AD9754 and the op amp, is also used to level-shift the differ- ential output of the AD9754 to midsupply (i.e., AVDD/2). The AD8041 is a suitable op amp for this application. ...
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... SINGLE-ENDED BUFFERED VOLTAGE OUTPUT CONFIGURATION Figure 31 shows a buffered single-ended output configuration in which the op amp U1 performs an I-V conversion on the AD9754 output current. U1 maintains IOUTA (or IOUTB virtual ground, thus minimizing the nonlinear output impedance effect on the DAC’s INL performance as discussed in the Analog Output section ...
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... OUT IN Proper grounding and decoupling should be a primary objective in any high speed, high resolution system. The AD9754 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. In general, AVDD, the analog supply, should be decoupled to ACOM, the analog common, as close to the chip as physi- cally possible ...
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... DAC (i.e., AD9754) tend to dominate thus contributing to the roll-off in its SFDR performance. However, unlike most DACs, which employ an R-2R ladder for the lower bit current segmentation, the AD9754 (as REV. A well as other TxDAC members) exhibits an improvement in distortion performance as the amplitude of a single tone is re- duced from its full-scale level ...
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... ACP to be above the spectral mask, then filtering, or different component selection is needed to meet the mask requirements. Figure 36 shows an example of the AD9754 used in a W-CDMA transmitter application using the AD6122 CDMA 3 V transmit- 1.0M ter IF subsystem. The AD6122 has functions, such as external ...
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... AD9754 in any application where high resolution, high speed conversion is required. This board allows the user the flexibility to operate the AD9754 in various configurations. Possible output configurations in- clude transformer coupled, resistor terminated, inverting/ noninverting and differential amplifier outputs ...
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... AD9754 Figure 38. Evaluation Board Schematic –20– REV. A ...
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... REV. A Figure 39. Silkscreen Layer—Top Figure 40. Component Side PCB Layout (Layer 1) –21– AD9754 ...
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... AD9754 Figure 41. Ground Plane PCB Layout (Layer 2) Figure 42. Power Plane PCB Layout (Layer 3) –22– REV. A ...
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... REV. A Figure 43. Solder Side PCB Layout (Layer 4) Figure 44. Silkscreen Layer—Bottom –23– AD9754 ...
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... AD9754 0.0118 (0.30) 0.0040 (0.10) 0.006 (0.15) 0.002 (0.05) SEATING PLANE OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead, 300 Mil SOIC (R-28) 0.7125 (18.10) 0.6969 (17.70 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00 PIN 1 0.1043 (2.65) 0.0926 (2.35) 0.0500 0.0192 (0.49) SEATING 0.0125 (0.32) (1.27) 0.0138 (0.35) PLANE BSC 0.0091 (0.23) 28-Lead Thin Shrink Small Outline (RU-28) 0 ...