AD9761 Analog Devices, AD9761 Datasheet - Page 12

• Manufacturer Part Number: AD9761
• Description: 10-Bit, Complete, 40 MSPS, dual Transmit D/A Converter
• Manufacturer: Analog Devices

Specifications of AD9761

• Resolution (bits): 10bit
• Dac Update Rate: 40MSPS
• Dac Settling Time: 35ns
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Par

REFERENCE CONTROL AMPLIFIER
The AD9761 also contains an internal control amplifier that is
used to simultaneously regulate both DACs’ full-scale output
current, I
the same voltage reference and control circuitry, excellent
gain matching is ensured. The control amplifier is configured
as a V-I converter as shown in Figure 7 such that its current
output, I
external resistor, R
over to the segmented current sources with the proper scaling
factor to set I
The control amplifier allows a wide (10:1) adjustment span
of I
62.5 µA and 625 µA. The wide adjustment span of I
provides several application benefits. The first benefit relates
directly to the power dissipation of the AD9761’s analog
supply, AVDD, which is proportional to I
Power Dissipation section). The second benefit relates to the
20 dB adjustment span, which may be useful for system gain
control purposes.
Optimum noise and dynamic performance for the AD9761 is
obtained with a 0.1 µF external capacitor installed between
COMP2 and AVDD. The bandwidth of the reference control
amplifier is limited to approximately 5 kHz with a 0.1 µF
capacitor installed. Since the –3 dB bandwidth corresponds
to the dominant pole and therefore its dominant time con-
stant, the settling time of the control amplifier to a stepped
reference input response can be easily determined. Note that
the output of the control amplifier, COMP2, is internally
compensated via a 50 pF capacitor, thus ensuring its stabil-
ity if no external capacitor is added.
AD9761
EXT.
V
REF
OUTFS
AVDD
R
SET
REF
Figure 7. External Reference Configuration
over a 1 mA to 10 mA range by setting I
OUTFS
, is determined by the ratio of the V
V
OUTFS
REF
I
. Since the I and Q I
REF
/R
=
SET
SET
as stated in Equation 3.
, as stated in Equation 4. I
REFIO
FSADJ
REFLO
AD1580
AD9761
+1.2V REF
1.2V
AVDD
OUTFS
OUT1
OUT2
+
AGND
COMP2
–
R
Figure 8. Single-Supply Gain Control Circuit
50pF
are derived from
OUTFS
AD7524
FB
DB7–DB0
0.1F
V
V
REFIO
REF
(refer to the
DD
REF
CURRENT
SOURCE
R
ARRAY
REF
SET
is copied
0.1V TO 1.2V
AVDD
AVDD
and an
between
OUTFS
V
REF
I
REF
/R
=
SET
–12–
REFIO
FSADJ
REFLO
Depending on the requirements of the application, I
can be adjusted by varying either R
reference mode, by varying the REFIO voltage. I
varied for a fixed R
varying the voltage of REFIO over its compliance range of
1.25 V to 0.10 V. REFIO can be driven by a single-supply
amplifier or DAC, thus allowing I
R
1 M, a simple, low cost R-2R ladder DAC configured in
the voltage mode topology may be used to control the gain.
This circuit is shown in Figure 8 using the AD7524 and an
external 1.2 V reference, the AD1580.
ANALOG OUTPUTS
As previously stated, both the I and Q DACs produce two
complementary current outputs that may be configured for
single-ended or differential operation. I
converted into complementary single-ended voltage outputs,
V
the DAC Transfer Function section by Equations 5 through
8. The differential voltage, V
and V
via a transformer or differential amplifier configuration.
Figure 9 shows an equivalent circuit of the AD9761’s I (or Q)
DAC output. It consists of a parallel array of PMOS current
sources in which each current source is switched to either
IOUTA or IOUTB via a differential PMOS switch. As a result,
the equivalent output impedance of IOUTA and IOUTB
remains quite high (i.e., >100 k and 5 pF).
IOUTA and IOUTB have a negative and positive voltage
compliance range that must be adhered to achieve optimum
performance. The negative output compliance range of –1 V is
set by the breakdown limits of the CMOS process. Operation
beyond this maximum limit may result in a breakdown of the
output stage.
SET
IOUTA
+1.2V REF
AD9761
Figure 9. Equivalent Circuit of the AD9761 DAC Output
. Since the input impedance of REFIO is approximately
IOUTB
and V
BAND LIMITING
, can also be converted to a single-ended voltage
CAPACITOR
OPTIONAL
IOUTB
+
–
COMP2
50pF
, via a load resistor, R
SET
by disabling the internal reference and
CURRENT
SOURCE
ARRAY
IDIFF
AVDD
AD9761
AVDD
, existing between V
IOUTA
R
LOAD
REF
SET
to be varied for a fixed
, or, in the external
IOUTA
LOAD
AVDD
IOUTB
R
, as described in
and I
LOAD
REF
IOUTB
IOUTA
REF
can be
REV. C
can be