AD760 Analog Devices, AD760 Datasheet - Page 6

• Manufacturer Part Number: AD760
• Description: 16/18-Bit Self-Calibrating Serial/Byte DACPORT
• Manufacturer: Analog Devices

Specifications of AD760

• Resolution (bits): 18bit
• Dac Update Rate: 167kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +15.75V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Byte,Ser

AD760
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY: Analog Devices defines inte-
gral nonlinearity as the maximum deviation of the actual, ad-
justed DAC output from the ideal analog output (a straight line
drawn from 0 to FS – 1 LSB) for any bit combination. This is
also referred to as relative accuracy.
DIFFERENTIAL NONLINEARITY: Differential nonlinearity
is the measure of the change in the analog output, normalized to
full scale, associated with a 1 LSB change in the digital input
code. Monotonic behavior requires that the differential linearity
error be greater than or equal to –1 LSB over the temperature
range of interest.
MONOTONICITY: A DAC is monotonic if the output either
increases or remains constant for increasing digital inputs with
the result that the output will always be a single-valued function
of the input.
GAIN ERROR: Gain error is a measure of the output error be-
tween an ideal DAC and the actual device output with all 1s
loaded after offset error has been adjusted out.
OFFSET ERROR: Offset error is a combination of the offset
errors of the voltage-mode DAC and the output amplifier and is
measured with all 0s loaded in the DAC.
BIPOLAR ZERO ERROR: When the AD760 is connected for
bipolar output and 10 . . . 000 is loaded in the DAC, the devia-
tion of the analog output from the ideal midscale value of 0 V is
called the bipolar zero error.
DRIFT: Drift is the change in a parameter (such as gain, offset
and bipolar zero) over a specified temperature range. The drift
temperature coefficient, specified in ppm/°C, is calculated by
measuring the parameter at T
the change in the parameter by the corresponding temperature
change.
TOTAL HARMONIC DISTORTION + NOISE: Total har-
monic distortion + noise (THD+N) is defined as the ratio of the
square root of the sum of the squares of the values of the har-
monics and noise to the value of the fundamental input fre-
quency. It is usually expressed in percent (%). THD+N is a
measure of the magnitude and distribution of linearity error, dif-
ferential linearity error, quantization error and noise. The distri-
bution of these errors may be different, depending upon the
amplitude of the output signal. Therefore, to be the most useful,
THD+N should be specified for both large and small signal am-
plitudes.
SIGNAL-TO-NOISE RATIO: The signal-to-noise ratio is
defined as the ratio of the amplitude of the output when a full-
scale signal is present to the output with no signal present. This
is measured in dB.
DIGITAL-TO-ANALOG GLITCH IMPULSE: This is the
amount of charge injected from the digital inputs to the analog
output when the inputs change state. This is measured at half
scale when the DAC switches around the MSB and as many as
possible switches change state, i.e., from 011 . . . 111 to
100 . . . 000.
DIGITAL FEEDTHROUGH: When the DAC is not selected
(i.e., CS is held high), high frequency logic activity on the digi-
tal inputs is capacitively coupled through the device to show up
as noise on the V
OUT
pin. This noise is digital feedthrough.
MIN
, 25°C and T
MAX
and dividing
–6–
THEORY OF OPERATION
The AD760 uses autocalibration circuitry to produce a true
16-bit DAC with typically 0.2 LSB Integral and Differential
Linearity Error and 0.5 LSB Offset Error. The block diagram
in Figure 2 shows the circuit components needed for calibration.
The MAIN DAC uses an array of bipolar current sources with
MOS current steering switches to develop a current propor-
tional to the applied digital word, ranging from 0 mA to 2 mA.
A segmented architecture is used, where the most significant
four data bits are thermometer decoded to drive 15 equal cur-
rent sources. The lesser bits are scaled using an R-2R ladder,
then applied together with the segmented sources to the sum-
ming node of the output amplifier. An extra LSB is included in
the MAIN DAC, for use during calibration.
The self-calibration architecture of the AD760 attempts to
reduce the linearity errors of its transfer function. The algorithm
first checks for bipolar or unipolar operation, calibrates either
bipolar zero or unipolar offset, and then removes the carry er-
rors (DNL errors) associated with the upper 6 bits (64 codes).
Once calibrated, the top six bits of a code entering the MAIN
DAC simultaneously address the RAM, calling up a correction
code that is then applied to the CALDAC. The output cur-
rents of both the MAIN DAC and CALDAC are combined in
the summing amplifier to produce the corrected output voltage.
In the first step of DNL calibration the output of the MAIN
DAC is set to the code just below the code to be calibrated.
The extra LSB in the MAIN DAC is turned on to find the ex-
trapolated value for the next code. The comparator is then
nulled using TRANSFER STD DAC. The voltage at V
has in effect been sampled at the code to be calibrated.
Next, the extra LSB is turned off and the MAIN DAC code is
incremented by one LSB. The comparator is once again
nulled, this time with the CALDAC, until the V
to equal the previously sampled output. The CALDAC code is
stored in RAM and the process is repeated for the next code.
REF OUT
BIP CLR
OR LBE
REF IN
LDAC
HBE
CLR
SER
UNI/
17
18
19
20
21
25
26
Figure 2. Functional Block Diagram
+10V
REF
CALOK
CS
16
1
9.95k
S
OR
DB0
14
IN
CAL
16/18-BIT DAC LATCH
CALIBRATION SEQUENCER
2
INPUT REGISTER
TRANSFER STD DAC
MSB/
LSB
OR
DB1
CALIBRATION DAC
13
16/18-BIT
MAIN DAC
–V
RAM
18/16
SERIAL
OR
DB2
12
3
EE
+V
4
CC
DB7
7
+V
5
LL
AD760
10k
10k
DGND
OUT
6
is adjusted
15
24
23
27
28
22
OUT
S
SPAN/
BIP
OFF
V
MUX
MUX
AGND
REV. A
OUT
OUT
OUT
IN