AD7840 Analog Devices, AD7840 Datasheet
AD7840
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AD7840 Summary of contents
Page 1
... MHz. The analog output from the AD7840 provides a bipolar output range The AD7840 is fully specified for dynamic per- formance parameters such as signal-to-noise ratio and harmonic distortion as well as for traditional dc specifications. Full power output signals kHz can be created ...
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... V (pk-pk OUT 3 SNR calculation includes distortion and noise components. 4 Using external sample-and-hold (see Testing the AD7840). 5 Measured with respect to REF IN and includes bipolar offset error. 6 For capacitive loads greater than 50 pF, a series resistor is required (see Internal Reference section). 7 Sample tested @ + ensure compliance. ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7840 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... A. 23 REF IN Voltage Reference Input. The reference voltage for the DAC is applied to this pin internally buffered before being applied to the DAC. The nominal reference voltage for correct operation of the AD7840 LDAC Load DAC. Logic Input. A new word is loaded into the DAC latch from the input latch on the falling edge of this signal (see Interface Logic Information section) ...
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... V reference required by the AD7840 REF IN. An alternate source of reference voltage for the AD7840 in systems which use both a DAC and an ADC is to use the REF OUT voltage of ADCs such as the AD7870 and AD7871. A circuit showing this arrangement is shown in Figure 20 ...
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... In this case, all 14 bits of data (appearing on data inputs D13 (MSB) through D0 (LSB)) are loaded to the AD7840 input latch at the same time. CS and WR control the loading of this data. These control signals are level-triggered; therefore, the input latch can be made transparent by holding both signals at a logic low level ...
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... Therefore, two bits in the stream are don’t cares since their value does not affect the input latch data. The order and position in which the AD7840 accepts the 14 bits of input data depends upon the FORMAT and JUSTIFY in- puts ...
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... AD7840 under control of the microcontroller and associated logic at a 100 kHz update rate. The output of the AD7840 is applied to a ninth order, 50 kHz, low-pass filter. The output of the filter is in turn applied to a 16-bit accurate digi- tizer. This digitizes the signal and the microcontroller generates an FFT plot from which the dynamic performance of the AD7840 can be evaluated ...
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... Some applications will require improved performance versus fre- quency from the AD7840. In these applications, a simple sample-and-hold circuit such as that outlined in Figure 12 will extend the very good performance of the AD7840 to 20 kHz. Figure 12. Sample-and-Hold Circuit Other applications will already have an inherent sample-and- hold function following the AD7840 ...
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... DAC latch be controlled by the microprocessor rather than the external timer. One option (for double-buffered interfacing decode the AD7840 LDAC from the address bus so that a write operation to the DAC latch (at a separate address than the input latch) updates the output. An example of this is shown in the 8086 interface of Figure 18 ...
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... The LDAC input of the AD7840 is connected to DGND so the update of the DAC latch takes place on the sixteenth falling edge of SCLK. As with the previous interface, the FORMAT pin of the AD7840 must be tied and the JUSTIFY pin tied to DGND. Figure 21. AD7840–DSP56000 Serial Interface – ...
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... SCK. The NEC7720 is programmed for the LSB to be the first bit in the serial data stream. Therefore, the AD7840 is set up with the FORMAT pin tied to DGND and the JUSTIFY pin tied Figure 23. AD7840–NEC7720 Serial Interface ...
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... PCB component grid. The board also contains a simple sample-and-hold circuit which can be used on the output of the AD7840 to extend the very good performance of the AD7840 over a wider frequency range. A second wire link (labelled LK2 on the PCB) connects V (SKT1) to either the output of this sample-and-hold circuit or directly to the output of the AD7840 ...
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... AD7840 Figure 25. Data Acquisition Circuit Using the AD7840 Figure 26. PCB Silkscreen for Figure 25 –14– REV. B ...
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... Figure 27. PCB Component Side Layout for Figure 25 REV. B Figure 28. PCB Solder Side Layout for Figure 25 –15– AD7840 ...
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... AD7840 Figure 29. SKT4, IDC Connector Pinout Figure 30. SKT5, D-Type Connector Pinout OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Plastic DIP (N-24) Ceramic DIP (D-24A) Cerdip (Q-24) PLCC (P-28A) –16– REV. B ...