AD7245A Analog Devices, AD7245A Datasheet - Page 10

• Manufacturer Part Number: AD7245A
• Description: 12-Bit DACPORT with Double-Buffered Parallel Input
• Manufacturer: Analog Devices

Specifications of AD7245A

• Resolution (bits): 12bit
• Dac Update Rate: 143kSPS
• Dac Settling Time: 7µs
• Max Pos Supply (v): +16.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Par

AD7245A/AD7248A
The LDAC input controls the transfer of 12-bit data from the
input latch to the DAC latch. This LDAC signal is also level
triggered, and data is latched into the DAC latch on the rising
edge of LDAC. The LDAC input is asynchronous and indepen-
dent of WR. This is useful in many applications especially in
the simultaneous updating of multiple AD7248A outputs. How-
ever, in systems where the asynchronous LDAC can occur during
a write cycle (or vice versa) care must be taken to ensure that
incorrect data is not latched through to the output. In other words,
if LDAC goes low while WR and either CS input are low (or
WR and either CS go low while LDAC is low), then the LDAC
signal must stay low for t
ensure correct data is latched through to the output. The write
cycle timing diagram for the AD7248A is shown in Figure 7.
An alternate scheme for writing data to the AD7248A is to tie
the CSMSB and LDAC inputs together. In this case exercising
CSLSB and WR latches the lower 8 bits into the input latch.
The second write, which exercises CSMSB, WR and LDAC
loads the upper 4-bit nibble to the input latch and at the same
time transfers the 12-bit data to the DAC latch. This automatic
transfer mode updates the output of the AD7248A in two write
operations. This scheme works equally well for CSLSB and
LDAC tied together provided the upper 4-bit nibble is loaded
to the input latch followed by a write to the lower 8 bits of
the input latch.
CSLSB CSMSB WR LDAC Function
L
L
g
H
H
H
H
H
H
H
H = High State, L = Low State
CSMSB
CSLSB
LDAC
DATA
WR
IN
H
H
H
L
L
g
H
H
L
H
t
3
t
t
1
2
t
VALID
Table II. AD7248A Truth Table
L
g
L
L
g
L
H
H
L
H
5
DATA
t
6
H
H
H
H
H
H
L
g
L
H
t
t
3
4
7
or longer after WR returns high to
Load LS Byte into Input Latch
Latches LS Byte into Input Latch
Latches LS Byte into Input Latch
Loads MS Nibble into Input Latch
Latches MS Nibble into Input Latch
Latches MS Nibble into Input Latch
Loads Input Latch into DAC Latch
Latches Input Latch into DAC Latch
Loads MS Nibble into Input Latch and
Loads Input Latch into DAC Latch
No Data Transfer Operation
t
t
1
2
t
VALID
5
DATA
t
6
t
4
t
7
5V
0V
5V
0V
5V
0V
5V
0V
5V
0V
APPLYING THE AD7245A/AD7248A
The internal scaling resistors provided on the AD7245A/
AD7248A allow several output voltage ranges. The part can
produce unipolar output ranges of 0 V to 5 V or 0 V to 10 V
and a bipolar output range of –5 V to +5 V. Connections for
the various ranges are outlined below.
UNIPOLAR (0 V TO 10 V) CONFIGURATION
The first of the configurations provides an output voltage range
of 0 V to 10 V. This is achieved by connecting the bipolar offset
resistor, R
configuration the AD7245A/AD7248A can be operated single
supply (V
required, a V
shows the connection diagram for unipolar operation while the
table for output voltage versus the digital code in the DAC latch
is shown in Table III.
DAC Latch Contents
MSB
1 1 1 1
1 0 0 0
1 0 0 0
0 1 1 1
0 0 0 0
0 0 0 0
NOTE: 1 LSB = 2
0.1 F
OMITTED FOR CLARITY
Table III. Unipolar Code Table (0 V to 10 V Range)
DIGITAL CIRCUITRY
SS
OFS
1 1 1 1
0 0 0 0
0 0 0 0
1 1 1 1
0 0 0 0
0 0 0 0
= 0 V = AGND). If dual supply performance is
REF
SS
REF OUT
, to AGND and connecting R
10 F
10
of –12 V to –15 V should be applied. Figure 8
V
REF
LSB
1 1 1 1
0 0 0 1
0 0 0 0
1 1 1 1
0 0 0 1
0 0 0 0
V
DGND
REF
DAC
(2
R
OFS
–12
2R
AD7245A/AD7248A
) = V
AGND
Analog Output, V
+2 V
+2 V
+2 V
+2 V
+2 V
REF
REF
REF
REF
REF
REF
V
DD



0 V
2048
2R
FB
V















SS
1
4095
4096
2049
4096
2048
4096
2047
4096
4096
to V
1



OUT







 = +V







R
OUT
FB
. In this
V
OUT
REF