AD8004 Analog Devices, AD8004 Datasheet - Page 10

• Manufacturer Part Number: AD8004
• Manufacturer: Analog Devices

Specifications of AD8004

• -3db Bandwidth: 250MHz
• Slew Rate: 3kV/µs
• Vos: 1mV
• Ib: 35µA
• # Opamps Per Pkg: 4
• Input Noise (nv/rthz): 1.5nV/rtHz
• Vcc-vee: 4V to 12V
• Isy Per Amplifier: 4.25mA
• Packages: DIP,SOIC

AD8004
DRIVING CAPACITIVE LOADS
The AD8004 was designed primarily to drive nonreactive loads.
If driving loads with a capacitive component is desired, best
settling response is obtained by the addition of a small series
resistance as shown in Figure 6. The accompanying graph shows
the optimum value for R
noting that the frequency response of the circuit when driving
large capacitive loads will be dominated by the passive roll-off of
R
Figure 7. Recommended R
£ 30 ns Settling to 0.1%
OPTIMIZING FLATNESS
The fine scale gain flatness and –3 dB bandwidth is affected by
R
With the exception of gain = +1, the AD8004 can be adjusted
for either maximal flatness with modest closed-loop bandwidth
or for mildly peaked-up frequency response with much more
bandwidth. Figure 8 shows the effect of three evenly spaced R
changes upon gain = +1 and gain = +2. Table I shows the
recommended component values for achieving maximally flat
frequency response as well as a faster slightly peaked-up fre-
quency response.
Printed circuit board parasitics and device lead frame parasitics
also control fine scale gain flatness. The AD8004R package,
because of its small lead frame, offers superior parasitics relative
to the N package. In the printed circuit board environment,
parasitics such as extra capacitance caused by two parallel and
vertical flat conductors on opposite PC board sides in the
SERIES
FEEDBACK
and C
40
30
20
10
1k
0
selection as is normal of current feedback amplifiers.
Figure 6. Driving Capacitive Load
L
.
5
SERIES
AD8004
1k
10
SERIES
C
vs. capacitive load. It is worth
L
– pF
vs. Capacitive Load for
R
15
SERIES
1k
R
L
20
C
L
25
F
–10–
region of the summing junction will cause some bandwidth
extension and/or increased peaking. In noninverting gains, the
effect of extra capacitance on summing junctions is far more
pronounced than with inverting gains. Figure 9 shows an example
of this. Note that only 1 pF of added junction capacitance causes
about a 70% bandwidth extension and additional peaking on a
gain = +2. For an inverting gain = –2, 5 pF of additional summing
junction capacitance caused a small 10% bandwidth extension.
Extra output capacitive loading also causes bandwidth exten-
sions and peaking. The effect is more pronounced with less
resistive loading from the next stage. Figure 10 shows the effect
of direct output capacitive loads for gains of +2 and –2. For both
gains C
For each of the four traces in Figure 10 the resistive loads were
100
lighter output resistive load. Note that even though bandwidth
is extended 2¥, the flatness dramatically suffers.
Figure 9. Frequency Response vs. Added Summing
Junction Capacitance
Figure 8. R
–10
–12
–14
. Figure 11 also shows capacitive loading effects with a
–2
–4
–6
–8
LOAD
–1
–2
–3
–4
–5
2
0
1
0
1
1
V
V
R
R PACKAGE
V
R
was set to 10 pF or 0 pF (no extra capacitive loading).
IN
S
L
IN
L
G = +2
5V
G = –2
G = +1
G = +2
=
= 100
= 100
= 50mV rms
FEEDBACK
= 50mV rms
S
5V
vs. Frequency Response, G = +1/+2
FREQUENCY – MHz
10
FREQUENCY – MHz
10
R
F
= 1.10k
R
F
40
= 1.1k
R
R
40
C
F
F
J
= 845
= 909
= 5.1pF
R
F
C
100
100
= 604
J
= 0
C
J
= 1pF
R
F
C
= 698
J
= 0
500
500
–2
–4
–6
–8
–1
–2
–3
–4
–5
–6
–7
–8
–10
–12
–14
REV. C
2
0
2
1
0