ADP8860 Analog Devices, ADP8860 Datasheet - Page 26

• Manufacturer Part Number: ADP8860
• Description: Charge Pump, 7-Channel Smart LED Driver with I2C Interface
• Manufacturer: Analog Devices

Specifications of ADP8860

• Vin Range: 2.4V to 5.5V
• Vout (v): 4.3 to 5.5
• Synchronous: No
• Package: 20-Lead WLCSP
• Led Configuration: Parallel
• Topology: Capacitive
• I2c Support: Yes
• Max Iout (ma): 60mA
• Brightness Control: I2C
• Peak Efficiency (%): 89%
• Switching Frequency: 1MHz

ADP8860
I
The ADP8860 provides full software programmability to
facilitate its adoption in various product architectures. The
default I
read). Therefore, the default write address is 0x54 and the read
address is 0x55.
Note the following general behavior of registers:
•
Table 7. Register Set Definitions
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
2
C PROGRAMMING AND DIGITAL CONTROL
All registers are set to their default values during reset or
after a UVLO event.
2
C address is 0101010x (x = 0 during write, x = 1 during
ST
Register Name
MFDVID
MDCR
MDCR2
INTR_EN
CFGR
BLSEN
BLOFF
BLDIM
BLFR
BLMX1
BLDM1
BLMX2
BLDM2
BLMX3
BLDM3
ISCFR
ISCC
ISCT1
ISCT2
ISCF
ISC7
ISC6
ISC5
ISC4
ISC3
ISC2
ISC1
CCFG
CCFG2
L2_TRP
L2_HYS
L3_TRP
0
1
0
CHIP ADDRESS
1
0
1
0
0 = WRITE
1 = READ
R/W
0
Figure 46. I
Description
Manufacturer and device ID
Device mode and status
Device mode and Status Register 2
Interrupts enable
Configuration register
Sink enable backlight or independent
Backlight off timeout
Backlight dim timeout
Backlight fade in and out rates
Backlight (Brightness Level 1—daylight) maximum current
Backlight (Brightness Level 1—daylight) dim current
Backlight (Brightness Level 2—office) maximum current
Backlight (Brightness Level 2—office) dim current
Backlight (Brightness Level 3—dark) maximum current
Backlight (Brightness Level 3—dark) dim current
Independent sink current fade control register
Independent sink current control register
Independent Sink Current Timer Register LED[7:5]
Independent Sink Current Timer Register LED[4:1]
Independent sink current fade register
Independent Sink Current LED7
Independent Sink Current LED6
Independent Sink Current LED5
Independent Sink Current LED4
Independent Sink Current LED3
Independent Sink Current LED2
Independent Sink Current LED1
Comparator configuration
Second comparator configuration
L2 comparator reference
L2 hysteresis
L3 comparator reference
Rev. 0 | Page 26 of 52
REG ADDRESS
2
C Command Sequence
•
•
The following tables provide register and bit descriptions. The
reset value for all bits in the bit map tables is all 0s, except in
Table 9 (see Table 9 for its unique reset value). Wherever the
acronym N/A appears in the tables, it means not applicable.
All registers are read/write unless otherwise specified.
Unused bits are read as zero.
0
DATA
0
SP