ADM1087 Analog Devices, ADM1087 Datasheet - Page 9

• Manufacturer Part Number: ADM1087
• Description: Voltage Sequencer with Active Low, Open-Drain Enable Output
• Manufacturer: Analog Devices

Specifications of ADM1087

• # Supplies Monitored: 1
• Volt Monitoring Accuracy: 7%
• # Output Drivers: 1
• Fet Drive/enable Output: Enable
• Sequencing: Up
• Package: 6 ld SC70

CIRCUIT INFORMATION
TIMING CHARACTERISTICS AND TRUTH TABLES
The enable outputs of the ADM1085/ADM1086/ADM1087/
ADM1088 are related to the V
AND function. The enable output is asserted only if the enable
input is asserted and the voltage at V
the time delay elapsed. Table 5 and Table 6 show the enable
output logic states for different V
when the capacitor delay has elapsed. The timing diagrams in
Figure 18 and Figure 19 give a graphical representation of how
the ADM1085/ADM1086/ADM1087/ADM1088 enable outputs
respond to V
Table 5. ADM1085/ADM1086 Truth Table
V
<V
<V
>V
>V
Table 6. ADM1087/ADM1088 Truth Table
V
<V
<V
>V
>V
ENOUT
ENOUT
IN
IN
ENIN
ENIN
TH_FALLING
TH_FALLING
TH_RISING
TH_RISING
TH_FALLING
TH_FALLING
TH_RISING
TH_RISING
V
V
IN
IN
Figure 18. ADM1085/ADM1086 Timing Diagram
Figure 19. ADM1087/ADM1088 Timing Diagram
IN
and enable input signals.
V
V
TH_RISING
TH_RISING
t
t
EN
EN
ENIN
0
1
0
1
ENIN
1
0
1
0
IN
and enable inputs by a simple
IN
/enable input combinations
IN
is above V
ENOUT
0
0
0
1
ENOUT
1
1
1
0
TH_RISING
V
V
TH_FALLING
TH_FALLING
, with
Rev. A | Page 9 of 16
When V
internal circuit generates a delay (t
is asserted. If V
(V
Similarly, if the enable input is disabled while V
threshold, the enable output deasserts immediately. Unlike V
a low-to-high transition on ENIN (or high-to-low on ENIN )
does not yield a time delay on ENOUT ( ENOUT ).
CAPACITOR-ADJUSTABLE DELAY CIRCUIT
Figure 20 shows the internal circuitry used to generate the time
delay on the enable output. A 250 nA current source charges a
small internal parasitic capacitance (C
voltage reaches 1.2 V, the enable output is asserted. The time
taken for the capacitor to reach 1.2 V, in addition to the propa-
gation delay of the comparator, constitutes the enable timeout,
which is typically 35 μs.
To minimize the delay between V
and the enable output deasserting, an NMOS transistor is
connected in parallel with C
detector is connected to the gate of this transistor so that, when
V
discharges quickly.
Connecting an external capacitor to the CEXT pin delays the
rise time—and therefore the enable timeout—further. The
relationship between the value of the external capacitor and the
resulting timeout is characterized by the following equation:
ADM1085/ADM1086/ADM1087/ADM1088
IN
SIGNAL FROM
TH_FALLING
DETECTOR
VOLTAGE
falls below V
t
EN
= (C × 4.8 ×10
IN
reaches the upper threshold voltage (V
), the enable output is deasserted immediately.
Figure 20. Capacitor-Adjustable Delay Circuit
IN
TH_FALLING
drops below the lower threshold voltage
C
INT
6
) + 35 μs
V
CC
, the transistor switches on and C
C
250nA
INT
CEXT
. The output of the voltage
1.2V
IN
EN
falling below V
) before the enable output
INT
). When the capacitor
IN
TO AND GATE
AND OUTPUT
STAGE
TH_RISING
is above the
TH_FALLING
), an
INT
IN
,