ADM1065 Analog Devices, ADM1065 Datasheet

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ADM1065

Manufacturer Part Number
ADM1065
Description
Manufacturer
Analog Devices
Datasheet

Specifications of ADM1065

# Supplies Monitored
10
Volt Monitoring Accuracy
1%
# Output Drivers
10
Fet Drive/enable Output
Both
Package
40 ld LFCSP ,48 ld TQFP

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADM1065ASUZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
ADM1065ASUZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
FEATURES
Complete supervisory and sequencing solution for up to
10 supply fault detectors enable supervision of supplies to
5 selectable input attenuators allow supervision of supplies to
5 dual-function inputs, VX1 to VX5 (VXx)
10 programmable driver outputs, PDO1 to PDO10 (PDOx)
Sequencing engine (SE) implements state machine control of
Device powered by the highest of VPx, VH for improved
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPx = 1.2 V
Available in 40-lead, 6 mm × 6 mm LFCSP and
APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies
For more information about the ADM1065 register map,
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
10 supplies
<1.0% accuracy across all voltages and temperatures
14.4 V on VH
6 V on VP1 to VP4 (VPx)
High impedance input to supply fault detector with
General-purpose logic input
Open-collector with external pull-up
Push/pull output driven to VDDCAP or VPx
Open collector with weak pull-up to VDDCAP or VPx
Internally charge-pumped high drive for use with external
PDO outputs
redundancy
48-lead, 7 mm × 7 mm TQFP packages
refer to the AN-698 Application Note at www.analog.com.
<0.5% accuracy at all voltages at 25°C
thresholds between 0.573 V and 1.375 V
N-FET (PDO1 to PDO6 only)
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
GENERAL DESCRIPTION
The ADM1065 Super Sequencer® is a configurable supervisory/
sequencing device that offers a single-chip solution for supply
monitoring and sequencing in multiple-supply systems.
The device also provides up to 10 programmable inputs for moni-
toring undervoltage faults, overvoltage faults, or out-of-window
faults on up to 10 supplies. In addition, 10 programmable outputs
can be used as logic enables. Six of these programmable outputs
can each provide up to a 12 V output for driving the gate of an
N-FET that can be placed in the path of a supply.
The logical core of the device is a sequencing engine. This state
machine-based construction provides up to 63 different states.
This design enables very flexible sequencing of the outputs
based on the condition of the inputs.
The ADM1065 is controlled via configuration data that can be
programmed into an EEPROM. The whole configuration can
be programmed using an intuitive GUI-based software package
provided by Analog Devices, Inc.
VDDCAP
Super Sequencer and Monitor
AGND
VX1
VX2
VX3
VX4
VX5
VP1
VP2
VP3
VP4
VH
ARBITRATOR
PROGRAMMABLE
(LOGIC INPUTS
FUNCTIONAL BLOCK DIAGRAM
GENERATORS
ADM1065
FUNCTION
VDD
INPUTS
RESET
DUAL-
(SFDs)
SFDs)
OR
©2004–2011 Analog Devices, Inc. All rights reserved.
VCCP
SEQUENCING
REFOUT REFGND
Figure 1.
ENGINE
GND
VREF
(HV CAPABLE OF
CONFIGURABLE
CONFIGURABLE
LOGIC SIGNALS)
SDA SCL A1
DRIVING GATES
(LV CAPABLE
OF DRIVING
OF N-FET)
DRIVERS
DRIVERS
OUTPUT
OUTPUT
ADM1065
INTERFACE
SMBus
www.analog.com
EEPROM
A0
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
PDO9
PDO10
PDOGND

Related parts for ADM1065

ADM1065 Summary of contents

Page 1

... This design enables very flexible sequencing of the outputs based on the condition of the inputs. The ADM1065 is controlled via configuration data that can be programmed into an EEPROM. The whole configuration can be programmed using an intuitive GUI-based software package provided by Analog Devices, Inc. ...

Page 2

... Changes to Figure 3.......................................................................... 7 Added Exposed Pad Notation to Outline Dimensions ............. 26 Changes to Ordering Guide .......................................................... 26 5/08—Rev Rev. C Changes to Table 1............................................................................ 4 Changes to Powering the ADM1065 Section ............................. 10 Changes to Default Output Configuration Section ................... 13 Changes to Sequence Detector Section ....................................... 15 Changes to Configuration Download at Power-Up Section..... 18 Changes to Table 9.......................................................................... 19 Changes to Figure 26...................................................................... 20 Changes to Figure 27 ...

Page 3

... SFD REG 5.25V CHARGE PUMP VDD GND VCCP Figure 2. Rev Page SMBus OSC DEVICE EEPROM CONFIGURABLE OUTPUT DRIVER PDO1 (HV) PDO2 PDO3 PDO4 PDO5 CONFIGURABLE OUTPUT DRIVER PDO6 (HV) CONFIGURABLE OUTPUT DRIVER PDO7 (LV) PDO8 PDO9 CONFIGURABLE OUTPUT DRIVER PDO10 (LV) PDOGND ADM1065 ...

Page 4

... ADM1065 SPECIFICATIONS 3 14 VPx = 3 6.0 V Table 1. Parameter POWER SUPPLY ARBITRATION VH, VPx VPx VH VDDCAP C VDDCAP POWER SUPPLY Supply Current VPx Additional Currents All PDO FET Drivers On Current Available from VDDCAP EEPROM Erase Current SUPPLY FAULT DETECTORS VH Pin Input Impedance Input Attenuator Error ...

Page 5

... Rev Page ADM1065 Test Conditions/Comments μ μ < V < (pull-up to VDDCAP or VPx VPx = 6 ≤ ...

Page 6

... ADM1065 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Voltage on VH Pin Voltage on VPx Pins Voltage on VXx Pins Voltage on A0, A1 Pins Voltage on REFOUT Pin Voltage on VDDCAP, VCCP Pins Voltage on PDOx Pins Voltage on SDA, SCL Pins Voltage on GND, AGND, PDOGND, REFGND Pins Input Current at Any Pin ...

Page 7

... INDICATOR VX2 3 VX3 4 VX4 5 ADM1065 VX5 6 TOP VIEW VP1 7 (Not to Scale) VP2 8 VP3 9 VP4 CONNECT Figure 4. TQFP Pin Configuration ADM1065 NC 36 PDO1 35 PDO2 34 PDO3 33 PDO4 32 PDO5 31 PDO6 30 PDO7 29 PDO8 28 PDO9 27 PDO10 ...

Page 8

... ADM1065 Pin No. 1 Mnemonic LFCSP TQFP 39 46 VDDCAP GND 1 Note that the LFCSP has an exposed pad on the bottom. This pad connect (NC). If possible, this pad should be soldered to the board for improved mechanical stability typical application, all ground pins are connected together. ...

Page 9

... VP1 Figure 8. I vs. V (VP1 Not as Supply) VP1 VP1 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0 (V) VH Figure 9. I vs. V (VH as Supply 350 300 250 200 150 100 (V) VH Figure 10. I vs. V (VH Not as Supply ADM1065 ...

Page 10

... ADM1065 2.5 5.0 7.5 I (µA) LOAD Figure 11. Charge-Pumped V (FET Drive Mode) vs. I PDO1 5.0 4.5 4.0 3.5 3.0 2.5 VP1 = 3V 2.0 1.5 1.0 0 (mA) LOAD Figure 12. V (Strong Pull-Up to VPx) vs. I PDO1 10.0 12.5 15.0 LOAD VP1 = LOAD Rev Page 4.5 4.0 3.5 VP1 = 5V 3.0 2.5 VP1 = 3V 2.0 1.5 1.0 0 ...

Page 11

... A supply comparator chooses the highest input to provide the on-chip supply. There is minimal switching loss with this architecture (~0.2 V), resulting in the ability to power the ADM1065 from a supply as low as 3.0 V. Note that the supply on the VXx pins cannot be used to power the device. An external capacitor to GND is required to decouple the on-chip supply from noise ...

Page 12

... Table 6 shows the details of each input. PROGRAMMING THE SUPPLY FAULT DETECTORS The ADM1065 can have SFDs on its 10 input channels. These highly programmable reset generators enable the supervision supply voltages. The supplies can be as low as 0.573 V and as high as 14 ...

Page 13

... VXx input pins on the ADM1065 have dual functionality. The second function digital logic input to the device. Therefore, the ADM1065 can be configured for up to five digital inputs. These inputs are TTL-/CMOS-compatible. Standard logic signals can be applied to the pins, RESET from reset generators, PWRGD signals, fault flags, manual resets, and more ...

Page 14

... All of the internal registers in an unprogrammed ADM1065 device from the factory are set to 0. Because of this, the PDOx pins are pulled to GND by a weak (20 kΩ) on-chip pull-down resistor. As the input supply to the ADM1065 ramps up on VPx or VH, all PDOx pins behave as follows: • ...

Page 15

... If VP2 is not okay State DIS3V3. PWRGD If VX1 is high State DIS2V5. MONITOR FAULT The ADM1065 offers state definitions. The signals monitored to indicate the status of the input pins are the outputs of the SFDs. WARNINGS The SE also monitors warnings. These warnings can be generated when the ADC readings violate their limit register value or when the secondary voltage monitors on VPx and VH are triggered ...

Page 16

... ADM1065 SEQUENCING ENGINE APPLICATION EXAMPLE The application in this section demonstrates the operation of the SE. Figure 22 shows how the simple building block of a single SE state can be used to build a power-up sequence for a three-supply system. Table 8 lists the PDO outputs for each state in the same SE implementation. In this system, a good 5 V supply on VP1 and the VX1 pin held low are the triggers required to start a power-up sequence ...

Page 17

... FAULT AND STATUS REPORTING FAULT The ADM1065 has a fault latch for recording faults. Two registers, FSTAT1 and FSTAT2, are set aside for this purpose. A single bit is assigned to each input of the device, and a fault on that input sets the relevant bit. The contents of the fault register can be read out over the SMBus to determine which input(s) faulted ...

Page 18

... ADM1065 APPLICATIONS DIAGRAM 12V ADM1065 5V OUT VP1 3V OUT VP2 3.3V OUT VP3 2.5V OUT VP4 1.8V OUT VX1 1.2V OUT VX2 0.9V OUT VX3 POWRON VX4 RESET VX5 VCCP VDDCAP 10µF 10µF IN DC-TO-DC1 EN OUT PDO1 PDO2 IN DC-TO-DC2 PDO3 PDO4 EN OUT PDO5 PWRGD PDO6 ...

Page 19

... EEPROM contents to the RAM again, as described in Option 3, restoring the ADM1065 to its original configuration. The topology of the ADM1065 makes this type of operation possible ...

Page 20

... Therefore, access to the ADM1065 is restricted until the download is complete. Identifying the ADM1065 on the SMBus The ADM1065 has a 7-bit serial bus slave address (see Table 9). The device is powered up with a default serial bus address. The five MSBs of the address are set to 01011; the two LSBs are determined by the logical states of Pin A1 and Pin A0 ...

Page 21

... ACK. BY SLAVE FRAME 1 COMMAND CODE ACK. BY SLAVE FRAME 3 DATA BYTE Figure 26. General SMBus Write Timing Diagram Rev Page ACK. BY SLAVE FRAME ACK. BY STOP BY SLAVE FRAME N MASTER DATA BYTE ADM1065 ...

Page 22

... ADM1065 1 SCL SDA START BY MASTER SLAVE ADDRESS 1 SCL (CONTINUED) SDA D7 D6 (CONTINUED SCL t HD; STA SDA t BUF R ACK. BY SLAVE FRAME ACK. BY MASTER FRAME 3 DATA BYTE Figure 27. General SMBus Read Timing Diagram ...

Page 23

... The slave asserts an ACK on SDA. 6. The master asserts a stop condition on SDA and the transaction ends. In the ADM1065, the send byte protocol is used for two purposes: • To write a register address to the RAM for a subsequent single byte read from the same address or for a block read or a block write starting at that address, as shown in Figure 29 ...

Page 24

... ADDRESS A P LOW BYTE Note that the ADM1065 features a clock extend function for writes to the EEPROM. Programming an EEPROM byte takes approxi- mately 250 μs, which limits the SMBus clock for repeated or block write operations. The ADM1065 pulls SCL low and extends the clock pulse when it cannot accept any more data ...

Page 25

... ADM1065 is correct. The PEC byte is an optional byte sent after the last data byte is written to or read from the ADM1065. The protocol is the same as a block read for Step 1 to Step 12 and then proceeds as follows: 13 ...

Page 26

... PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE 1.05 1.00 0.95 0.15 0.05 ROTATED 90° CCW ORDERING GUIDE Model 1 Temperature Range ADM1065ACPZ −40°C to +85°C ADM1065ASUZ −40°C to +85°C EVAL-ADM1065TQEBZ RoHS Compliant Part. 6.00 BSC SQ 0.60 MAX 0.50 TOP BSC 5.75 VIEW BSC SQ 0.50 0.40 0.30 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 COPLANARITY 0.20 REF ...

Page 27

... NOTES Rev Page ADM1065 ...

Page 28

... ADM1065 NOTES ©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04634-0-6/11(D) Rev Page ...

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