ADP123 Analog Devices, ADP123 Datasheet - Page 5

• Manufacturer Part Number: ADP123
• Description: 5.5 V Input, 300 mA, Low Quiescent Current, CMOS Linear Regulator, Adjustable Output Voltage
• Manufacturer: Analog Devices

ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND
ADJ to GND
EN to GND
VOUT to GND
Storage Temperature Range
Operating Ambient Temperature Range
Operating Junction Temperature
Soldering Conditions
Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating
only; functional operation of the device at these or any other
conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP122/ADP123 can be damaged when the
junction temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that T
specified temperature limits. In applications with high power
dissipation and poor thermal resistance, the maximum ambient
temperature may have to be derated.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. The junction temperature (T
the device is dependent on the ambient temperature (T
power dissipation of the device (P
thermal resistance of the package (θ
Maximum junction temperature (T
ambient temperature (T
formula
The junction-to-ambient thermal resistance (θ
is based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on the
T
J
= T
A
+ (P
D
× θ
JA
)
A
) and power dissipation (P
D
), and the junction-to-ambient
JA
J
) is calculated from the
).
J
will remain within the
Rating
−0.3 V to +6.5 V
−0.3 V to +4 V
−0.3 V to +6.5 V
−0.3 V to VIN
−65°C to +150°C
−40°C to +85°C
−40°C to +125°C
JEDEC J-STD-020
JA
) of the package
D
) using the
A
), the
J
) of
Rev. A | Page 5 of 24
application and board layout. In applications in which high maxi-
mum power dissipation exists, close attention to thermal board
design is required. The value of θ
material, layout, and environmental conditions. The specified
values of θ
Refer to JESD51-7 for detailed information on the board
construction
Ψ
and is measured in °C/W. The Ψ
modeling and calculation using a 4-layer board. The Guidelines for
Reporting and Using Package Thermal Information: JESD51-12
states that thermal characterization parameters are not the same
as thermal resistances. Ψ
through multiple thermal paths rather than a single path as in
thermal resistance, θ
convection from the top of the package as well as radiation from
the package—factors that make Ψ
applications. Maximum junction temperature (T
from the board temperature (T
using the formula
Refer to JESD51-8 and JESD51-12 for more detailed information
about Ψ
THERMAL RESISTANCE
θ
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
5-Lead TSOT
6-Lead 2 mm × 2 mm LFCSP
ESD CAUTION
JA
JB
and Ψ
is the junction-to-board thermal characterization parameter
T
J
= T
JB
.
JB
JA
B
are specified for the worst-case conditions, that is, a
are based on a 4-layer, 4 inch × 3 inch circuit board.
+ (P
D
× Ψ
JB
. Therefore, Ψ
JB
)
JB
measures the component power flowing
B
JA
) and power dissipation (P
JB
may vary, depending on PCB
JB
of the package is based on
more useful in real-world
JB
thermal paths include
ADP122/ADP123
θ
170
68.9
JA
Ψ
43
44.1
J
) is calculated
JB
Unit
°C/W
°C/W
D
)