ADP5023

Manufacturer Part NumberADP5023
DescriptionDual 3 MHz, 800 mA Buck Regulator with One 300 mA LDO
ManufacturerAnalog Devices
ADP5023 datasheet
 


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Data Sheet
FEATURES
Main input voltage range: 2.3 V to 5.5 V
Two 800 mA buck regulators and one 300 mA LDO
24-lead, 4 mm × 4 mm LFCSP package
Regulator accuracy: ±3%
Factory programmable or external adjustable VOUTx
3 MHz buck operation with forced PWM and auto PWM/PSM
modes
BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V
LDO: output voltage range from 0.8 V to 5.2 V
LDO: input supply voltage from 1.7 V to 5.5 V
LDO: high PSRR and low output noise
APPLICATIONS
Power for processors, ASIC, FPGAs, and RF chipsets
Portable instrumentation and medical devices
Space constrained devices
2.3V TO
5.5V
1.7V TO
5.5V
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Regulators with One 300 mA LDO
GENERAL DESCRIPTION
The
ADP5023
and one low dropout (LDO) regulator in a small, 24-lead 4 mm ×
4 mm LFCSP to meet demanding performance and board space
requirements.
The high switching frequency of the buck regulators enables tiny
multilayer external components and minimizes the board space.
When the MODE pin is set high, the buck regulators operate in
forced PWM mode. When the MODE pin is set low, the buck
regulators operate in PWM mode when the load current is
above a predefined threshold. When the load current falls below
a predefined threshold, the regulator operates in power save
mode (PSM) improving the light-load efficiency.
The two bucks operate out of phase to reduce the input capaci-
tor requirement. The low quiescent current, low dropout voltage,
and wide input voltage range of the
battery life of portable devices. The
power supply rejection greater than 60 dB for frequencies as
high as 10 kHz while operating with a low headroom voltage.
Regulators in the
enable pins. The default output voltages can be externally set in
the adjustable version or factory programmable to a wide range
of preset values in the fixed voltage version.
TYPICAL APPLICATION CIRCUIT
AVIN
HOUSEKEEPING
C
FILT
VOUT1
0.1µF
VIN1
SW1
C1
FB1
BUCK1
4.7µF
PGND1
ON
EN1
EN1
OFF
MODE
MODE
VOUT2
VIN2
MODE
SW2
C2
4.7µF
BUCK2
FB2
EN2
EN2
PGND2
ON
OFF
EN3
VOUT3
EN3
VIN3
FB3
LDO
C3
1µF
ADP5023
AGND
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
Dual 3 MHz, 800 mA Buck
ADP5023
combines two high performance buck regulators
ADP5023
LDO extends the
ADP5023
LDO maintains
ADP5023
are activated though dedicated
L1 1µH
V
AT
OUT1
800mA
R1
C5
10µF
R2
PWM
PSM/PWM
L2 1µH
V
AT
OUT2
800mA
R3
C6
R4
10µF
V
AT
OUT3
300mA
R5
C7
1µF
R6
www.analog.com
©2011-2012 Analog Devices, Inc. All rights reserved.

ADP5023 Summary of contents

  • Page 1

    ... AGND Figure 1. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 Dual 3 MHz, 800 mA Buck ADP5023 combines two high performance buck regulators ADP5023 LDO extends the ADP5023 LDO maintains ADP5023 are activated though dedicated L1 1µ OUT1 800mA R1 C5 10µ ...

  • Page 2

    ... ADP5023 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Typical Application Circuit ............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 General Specifications ................................................................. 3 BUCK1 and BUCK2 Specifications ........................................... 4 LDO Specifications ...................................................................... 5 Input and Output Capacitor, Recommended Specifications .. 5 Absolute Maximum Ratings ............................................................ 6 Thermal Resistance ...................................................................... 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 8 REVISION HISTORY 1/12— ...

  • Page 3

    ... T = −40°C to +85°C SHUTDOWN J UVLO VIN1RISE UVLO VIN1FALL UVLO VIN1RISE UVLO VIN1FALL to VOUT1, VOUT2, and VOUT3 reaching 90% of their nominal level. Start-up times are AVIN Rev Page ADP5023 = 25°C for A Min Typ Max Unit 2.3 5.5 V 150 °C 20 °C 250 µs 300 µ ...

  • Page 4

    ... ADP5023 BUCK1 AND BUCK2 SPECIFICATIONS 2 5 −40°C to +125°C for minimum/maximum specifications, and T AVIN IN1 IN2 J specifications, unless otherwise noted. 1 Table 2. Parameter Symbol OUTPUT CHARACTERISTICS Output Voltage Accuracy ΔV /V OUT1 ΔV /V OUT2 Line Regulation (ΔV /V OUT1 (ΔV /V OUT2 Load Regulation (Δ ...

  • Page 5

    ... V 100 OUT3 = 2 OUT3 = 2 OUT3 = 2 OUT3 Min Typ Max 4.7 40 MIN2 10 40 MIN2 1.0 MIN4 0.001 1 ADP5023 Max Unit 5 µA 100 µA 245 µA µ +0. 0.003 %/mA 0.515 V mV 140 Ω µV rms dB dB ...

  • Page 6

    ... ADP5023 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter AVIN to AGND VIN1, VIN2 to AVIN PGND1, PGND2 to AGND VIN3, VOUT1, VOUT2, FB1, FB2, FB3, EN1, EN2, EN3, MODE to AGND VOUT3 to AGND SW1 to PGND1 SW2 to PGND2 Storage Temperature Range Operating Junction Temperature Range Soldering Conditions Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only ...

  • Page 7

    ... LDO Enable Pin. High level turns on this regulator, and low level turns it off. 23 AGND Analog Ground. 24 AGND Analog Ground. EPAD (EP) Exposed Pad recommended that the exposed pad be soldered to the ground plane. ADP5023 TOP VIEW (Not to Scale) Figure 2. Pin Configuration—View from Top of Die Rev Page ADP5023 ...

  • Page 8

    ... ADP5023 TYPICAL PERFORMANCE CHARACTERISTICS 3 25°C, unless otherwise noted. IN1 IN2 IN3 A 140 120 100 2.3 2.8 3.3 3.8 4.3 INPUT VOLTAGE (V) Figure 3. System Quiescent Current vs. Input Voltage 1 1 3.3 V, All Channels Unloaded OUT2 OUT3 OUT4 IOUT 2 VOUT 50.0mA Ω ...

  • Page 9

    ... OUT2 100 0.001 0.01 0.1 I (A) OUT V = 0.8 V, Auto Mode OUT1 100 0.001 0.01 0.1 I (A) OUT V = 0.8 V, PWM Mode OUT1 ADP5023 ...

  • Page 10

    ... ADP5023 100 0.001 0.01 I (A) OUT Figure 15. BUCK1 Efficiency vs. Load Current, Across Temperature 3 3.3 V, Auto Mode IN OUT1 100 0.001 0.01 I (A) OUT Figure 16. BUCK2 Efficiency vs. Load Current, Across Temperature 1.8 V, Auto Mode ...

  • Page 11

    ... CH1 50.0mV CH2 M 20.0µs A CH2 CH4 5.00V T 60.000µs OUT1 V = 3.3 V, Auto Mode OUT1 VOUT 1 I OUT 2 50.0mA Ω CH1 50.0mV CH2 M 20.0µs A CH2 CH4 5.00V T 22.20% OUT2 V = 1.8 V, Auto Mode OUT2 ADP5023 4.80V = 4 5.0 V, 356mA = mA, 379mA = mA, ...

  • Page 12

    ... ADP5023 VOUT 1 I OUT 2 CH2 200mA Ω CH1 50.0mV M 20.0µs A CH2 CH4 5.00V T 20.40% Figure 27. BUCK1 Response to Load Transient 3.3 V, Auto Mode OUT1 VOUT 1 I OUT 2 CH2 200mA Ω CH1 100mV M 20.0µs A CH2 CH4 5.00V T 19.20% Figure 28. BUCK2 Response to Load Transient ...

  • Page 13

    ... I (A) OUT IN3 T I OUT 2 VOUT 1 CH2 100mA Ω CH1 100mV M 40.0µs A CH2 T 19.20% OUT3 V = 2.8 V OUT3 T VIN VOUT CH1 20.0mV M 100µs A CH3 CH3 1.00V T 28.40 ADP5023 0. 2.8 V OUT3 52.0mA = mA, 4.80V = 2.8 V OUT3 ...

  • Page 14

    ... ADP5023 3. 0.001 0.01 0 (mA) OUT Figure 39. LDO Output Noise vs. Load Current, Across Input Voltage 2.8 V OUT3 3. 0.001 0.01 0 (mA) OUT Figure 40. LDO Output Noise vs. Load Current, Across Input Voltage 3.0 V OUT3 0 100µ ...

  • Page 15

    ... SW (2b the duty cycle. ADP5023 power switch conductive losses, the switch losses, and the transi- tion losses of each channel. There are other sources of loss, but these are generally less significant at high output load currents, where the thermal limit of the application is. Equation 8 captures the calculation that must be made to estimate the power dissipation in the buck regulator ...

  • Page 16

    ... RISE FALL switching node, SW. For the ADP5023, the rise and fall times of SW are in the order of 5 ns. If the preceding equations and parameters are used for estimat- ing the converter efficiency, it must be noted that the equations do not describe all of the converter losses, and the parameter values given are typical numbers ...

  • Page 17

    ... ADP5023 GM ERROR AMP PWM COMP SOFT START I LIMIT PSM COMP PWM/ PSM CONTROL LOW BUCK2 CURRENT DRIVER AND ANTISHOOT THROUGH OPMODE SEL MODE2 600Ω ENLDO VOUT3 ADP5023 has individual enable pins (EN1 to EN3) control- ADP5023 VIN2 SW2 PGND2 MODE ...

  • Page 18

    ... A logic level high applied to the ENx pin activates a regulator, whereas a logic level low turns off a regulator. Figure 46 shows the regulator activation timings for the ADP5023 shown is the active pull-down activation. Figure 46. Regulator Sequencing on ADP5023 ( EN1 = EN2 = EN3 Rev Page voltage level. The typical value of V POR has an individual control pin for each regulator ...

  • Page 19

    ... At this limit, the buck transitions to a mode where the pFET switch stays on 100% of the time. When Rev Page ADP5023 has a dedicated MODE pin controlling the PSM ensures that both bucks operate at the same ADP5023 ensures that when both bucks are ...

  • Page 20

    ... Figure 46 shows the activation timings for the active pull-downs during regulator activation and deactivation. LDO The ADP5023 contains one LDO with low quiescent current and low dropout voltage, and provides up to 300 mA of output current. Drawing a low 10 μA quiescent current (typical load makes the LDO ideal for battery-operated portable equipment ...

  • Page 21

    ... Figure 49. Capacitance vs. Voltage Characteristic Dimensions (mm) 2.0 × 1.6 × 0.9 3.2 × 2.5 × 1.5 3.2 × 2.5 × 2.5 4.0 × 4.0 × 2.1 1.9 × 2.0 × 1.0 2.5 × 2.0 × 1.2 Rev Page ADP5023 × (1 − TEMPCO) × (1 − TOL) OUT is 9.2 μ shown in Figure 49. OUT BIAS VOLTAGE (V) I (mA) DCR (mΩ ...

  • Page 22

    ... MODE SW2 C2 4.7µF BUCK2 FB2 EN2 EN2 ON PGND2 OFF EN3 VOUT3 EN3 LDO VIN3 FB3 (ANALOG) C3 1µF ADP5023 AGND Rev Page Data Sheet Case Type Model Size X5R GRM188R60J106 0603 X5R C1608JB0J106K 0603 X5R ECJ1VB0J106M 0603 Case Type Model ...

  • Page 23

    ... Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP5023 imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors are evaluated for each application. ...

  • Page 24

    ... ADP5023 PCB LAYOUT GUIDELINES Poor layout can affect ADP5023 performance, causing electro- magnetic interference (EMI) and electromagnetic compatibility (EMC) problems, ground bounce, and voltage losses. Poor layout can also affect regulation and stability. A good layout is implemented using the following guidelines. Also, refer to User Guide UG-271. • ...

  • Page 25

    ... PGND2 OFF EN3 VOUT3 EN3 LDO VIN3 FB3 (ANALOG) C3 1µF ADP5023 AGND Figure 53. ADP5023 Adjustable Output Voltages with Enable Pins Rev Page ADP5023 L1 1µ OUT1 800mA C5 10µF PWM PSM/PWM L2 1µ OUT2 800mA C6 10µF ...

  • Page 26

    ... Part Number Vendor JMK105BJ104MV-F Taiyo-Yuden LMK105BJ105MV-F Taiyo-Yuden ECJ-0EB0J475M Panasonic-ECG JMK107BJ106MA-T Taiyo-Yuden BRC1608T1R0M Taiyo-Yuden LQM2MPN1R0NG0B Murata EPL2014-102ML Coilcraft MDT2520-CN Toko ADP5023 Analog Devices Rev Page Data Sheet Package or Dimension (mm) 0402 0402 0402 0603 0603 2.0 × 1.6 × 0.9 2.0 × 2.0 × 1.4 2.5 × 2.0 × 1.2 24-lead LFCSP ...

  • Page 27

    ... VOUT1 = 1.2 V Low Enabled on VOUT2 = 3.3 V buck channels VOUT3 = 2.8 V Additional options available are: Rev Page 2.20 2. 0.25 MIN 4 Package Description 24-Lead Frame Chip Scale Package [LFCSP_WQ] 24-Lead Frame Chip Scale Package [LFCSP_WQ] Evaluation Board for ADP5023ACPZ-R7 ADP5023 Package Option CP-24-10 CP-24-10 ...

  • Page 28

    ... ADP5023 NOTES ©2011-2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09889-0-1/12(A) Rev Page Data Sheet ...