ADP1882 Analog Devices, ADP1882 Datasheet - Page 27

• Manufacturer Part Number: ADP1882
• Description: Synchronous Current-Mode Buck Controller with Constant On-time and 0.8 V Reference Voltage
• Manufacturer: Analog Devices

Diode Conduction Loss
The ADP1882/ADP1883 employ anticross conduction circuitry
that prevents the upper-side and lower-side MOSFETs from
conducting current simultaneously. This overlap control is
beneficial, avoiding large current flow that may lead to
irreparable damage to the external components of the power
stage. However, this blanking period comes with the trade-off of
a diode conduction loss occurring immediately after the
MOSFETs change states and continuing well into idle mode.
The amount of loss through the body diode of the lower-side
MOSFET during the antioverlap state is given by the following
expression:
where:
t
dead time periods).
t
V
(refer to the selected external MOSFET data sheet for more
information about the V
Inductor Loss
During normal conduction mode, further power loss is caused
by the conduction of current through the inductor windings,
which have dc resistance (DCR). Typically, larger sized inductors
have smaller DCR values.
The inductor core loss is a result of the eddy currents generated
within the core material. These eddy currents are induced by the
changing flux, which is produced by the current flowing through
the windings. The amount of inductor core loss depends on the
core material, the flux swing, the frequency, and the core volume.
Ferrite inductors have the lowest core losses, whereas powdered
iron inductors have higher core losses. It is recommended to use
shielded ferrite core material type inductors with the ADP1882/
ADP1883 for a high current, dc-to-dc switching application
BODY(LOSS)
SW
F
is the forward drop of the body diode during conduction
is the period per switching cycle.
Figure 82. Body Diode Conduction Time vs. Low Voltage Input (V
P
BODY
80
72
64
56
48
40
32
24
16
8
2.7
is the body conduction time (refer to Figure 82 for
(
LOSS
)
=
t
BODY
3.4
t
SW
(
LOSS
F
1MHz
300kHz
parameter).
)
×
I
V
LOAD
DD
4.1
(V)
×
V
F
×
2
4.8
+125°C
+25°C
–40°C
5.5
DD
)
Rev. 0 | Page 27 of 40
to achieve minimal loss and negligible electromagnetic
interference (EMI).
INPUT CAPACITOR SELECTION
The goal in selecting an input capacitor is to reduce or minimize
input voltage ripple and to reduce the high frequency source
impedance, which is essential for achieving predictable loop
stability and transient performance.
The problem with using bulk capacitors, other than their
physical geometries, is their large equivalent series resistance
(ESR) and large equivalent series inductance (ESL). Aluminum
electrolytic capacitors have such high ESR that they cause
undesired input voltage ripple magnitudes and are generally not
effective at high switching frequencies.
If bulk capacitors are to be used, it is recommended that multi-
layered ceramic capacitors (MLCC) be used in parallel, due to
their low ESR values. This dramatically reduces the input voltage
ripple amplitude as long as the MLCCs are mounted directly across
the drain of the upper-side MOSFET and the source terminal of
the lower-side MOSFET (see the Layout Considerations section).
Improper placement and mounting of these MLCCs may cancel
their effectiveness due to stray inductance and an increase in
trace impedance.
The maximum input voltage ripple and maximum input capacitor
rms current occur at the end of the duration of 1 − D while the
upper-side MOSFET is in the off state. The input capacitor rms
current reaches its maximum at Time D. When calculating the
maximum input voltage ripple, account for the ESR of the input
capacitor as follows:
where:
V
I
ESR is the equivalent series resistance rating of the input
capacitor used.
Inserting V
calculate the minimum input capacitor requirement gives
or
where D = 50%.
LOAD,MAX
RIPP
P
V
C
C
I
is usually 1% of the minimum voltage input.
DCR(LOSS)
CIN
MAX,RIPPLE
IN,min
IN,min
is the maximum load current.
,
RMS
=
MAX,RIPPLE
=
=
V
= DCR × I
I
MAX
4
LOAD
I
= V
LOAD
f
SW
,
I
RIPPLE
,
RIPP
MAX
LOAD
V
,
into the charge balance equation to
MAX
MAX
+ (I
,
×
MAX
2
×
LOAD
D
,
RIPPLE
LOAD,MAX
1 (
f
V
SW
−
+ Core Loss
OUT
D
)
×
V
× ESR)
ADP1882/ADP1883
(
V
OUT
IN
−
V
OUT
)