MCP6544-E/SL Microchip Technology, MCP6544-E/SL Datasheet - Page 14

• Manufacturer Part Number: MCP6544-E/SL
• Description: IC COMP 1.6V QUAD P-P 14SOIC
• Manufacturer: Microchip Technology
• Type: General Purposer

Specifications of MCP6544-E/SL

• Output Type: CMOS, Push-Pull, Rail-to-Rail, TTL
• Package / Case: 14-SOIC (0.154", 3.90mm Width)
• Number Of Elements: 4
• Voltage - Supply: 1.6 V ~ 5.5 V
• Mounting Type: Surface Mount
• Number Of Channels: 4 Channels
• Product: Analog Comparators
• Offset Voltage (max): 7 mV
• Input Bias Current (max): 0.000001 uA
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MCP6541/1R/1U/2/3/4
4.0
The MCP6541/1R/1U/2/3/4 family of push-pull output
comparators are fabricated on Microchip’s state-of-the-
art CMOS process. They are suitable for a wide range
of applications requiring very low power consumption.
4.1
4.1.1
The MCP6541/1R/1U/2/3/4 comparator family uses
CMOS transistors at the input. They are designed to
prevent phase inversion when the input pins exceed
the supply voltages.
exceeding both supplies with no resulting phase
inversion.
4.1.2
The ESD protection on the inputs can be depicted as
shown in
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
V
above V
allow normal operation, and low enough to bypass ESD
events within the specified limits.
FIGURE 4-1:
Structures.
In order to prevent damage and/or improper operation
of these amplifiers, the circuits they are in must limit the
currents (and voltages) at the V
Absolute Maximum Ratings † at the beginning of
Section 1.0 “Electrical Characteristics”).
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(V
the resistors R
out of the input pin. Diodes D
pin (V
When implemented as shown, resistors R
limit the current through D
DS21696F-page 14
SS
IN
. They also clamp any voltages that go too far
+ and V
V
V
V
IN
IN
DD
SS
+
+ and V
DD
APPLICATIONS INFORMATION
Comparator Inputs
Figure
; their breakdown voltage is high enough to
Bond
Bond
Bond
PHASE REVERSAL
INPUT VOLTAGE AND CURRENT
LIMITS
Pad
Pad
Pad
IN
–) from going too far below ground, and
1
and R
IN
4-1. This structure was chosen to
–) from going too far above V
Figure 2-3
2
Simplified Analog Input ESD
limit the possible current drawn
Stage
Input
1
and D
1
and D
shows an input voltage
IN
+ and V
2
.
2
Bond
prevent the input
Pad
1
IN
and R
– pins (see
Figure 4-3
V
IN
–
2
also
DD
.
FIGURE 4-2:
Inputs.
It is also possible to connect the diodes to the left of the
resistors R
the diodes D
mechanism. The resistor then serves as in-rush current
limiter; the DC current into the input pins (V
V
A significant amount of current can flow out of the
inputs when the common mode voltage (V
ground (V
high impedance may need to limit the useable voltage
range.
4.1.3
The input stage of this family of devices uses two
differential input stages in parallel: one operates at low
input voltages and the other at high input voltages. With
this topology, the input voltage is 0.3V above V
0.3V below V
measured at both V
proper operation.
The MCP6541/1R/1U/2/3/4 family has internally-set
hysteresis that is small enough to maintain input offset
accuracy (<7 mV) and large enough to eliminate output
chattering caused by the comparator’s own input noise
voltage (200 µV
IN
–) should be very small.
V
V
1
2
R
R
SS
1
1
2
NORMAL OPERATION
and R
1
R
≥
≥
); see
R
SS
and D
1
D
2
V
V
p-p
. Therefore, the input offset voltage is
1
SS
SS
D
).
2
– (minimum expected V
– (minimum expected V
SS
. In this case, the currents through
2
Figure
2
Figure 4-3
need to be limited by some other
- 0.3V and V
Protecting the Analog
© 2007 Microchip Technology Inc.
2-37. Applications that are
2 mA
MCP6G0X
2 mA
+
–
R
V
3
depicts this behavior.
DD
DD
+ 0.3V to ensure
CM
1
2
)
V
)
) is below
OUT
IN
DD
+ and
and