STM8L151K4 STMicroelectronics, STM8L151K4 Datasheet - Page 57

• Manufacturer Part Number: STM8L151K4
• Description: STM8L-Ultra Low Power-8 bits Microcontrollers
• Manufacturer: STMicroelectronics

Specifications of STM8L151K4

• Temp. Range: - 40 °C to 85, 105 or 125 °C
• 5 Low Power Modes: Wait, Low power run (5.1 μA), Low power wait (3 μA), Active-halt with full RTC (1.3 μA), Halt (350 nA)
• Consumption: 195 μA/MHz+440μA
• Ultralow Leakage Per I/0: 50 nA
• Fast Wakeup From Halt: 4.7 μs
• Lcd: up to 4x28 segments w/ step-up converter
• 4 Channels; Supported Peripherals: ADC, DAC, SPI, I2C, USART, timers
• 2 Watchdogs: 1 Window, 1 Independent

STM8L151xx, STM8L152xx
Table 13.
Option
OPT0
OPT1
OPT2
OPT3
OPT4
byte
No.
ROP[7:0] Memory readout protection (ROP)
UBC[7:0] Size of the user boot code area
Reserved
IWDG_HW: Independent watchdog
IWDG_HALT: Independent window watchdog off on Halt/Active-halt
WWDG_HW: Window watchdog
WWDG_HALT: Window window watchdog reset on Halt/Active-halt
HSECNT: Number of HSE oscillator stabilization clock cycles
LSECNT: Number of LSE oscillator stabilization clock cycles
Refer to
Option byte description
0xAA: Disable readout protection (write access via SWIM protocol)
Refer to Readout protection section in the STM8L15x and STM8L16x reference manual (RM0031).
0x00: no UBC
0x01: the UBC contains only the interrupt vectors.
0x02: Page 0 and 1 reserved for the UBC and read/write protected. Page 0 contains only the interrupt
vectors.
0x03 - Page 0 to 2 reserved for UBC, memory write-protected
0xFF - Page 0 to 254 reserved for UBC, memory write-protected
Refer to User boot code section in the STM8L15x and STM8L16x reference manual (RM0031).
0: Independent watchdog activated by software
1: Independent watchdog activated by hardware
0: Independent watchdog continues running in Halt/Active-halt mode
1: Independent watchdog stopped in Halt/Active-halt mode
0: Window watchdog activated by software
1: Window watchdog activated by hardware
0: Window watchdog stopped in Halt mode
1: Window watchdog generates a reset when MCU enters Halt mode
0x00 - 1 clock cycle
0x01 - 16 clock cycles
0x10 - 512 clock cycles
0x11 - 4096 clock cycles
0x00 - 1 clock cycle
0x01 - 16 clock cycles
0x10 - 512 clock cycles
0x11 - 4096 clock cycles
Table 32: LSE oscillator characteristics on page
Doc ID 15962 Rev 9
Option description
79.
Option bytes
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