MAX9022ASA+ Maxim Integrated Products, MAX9022ASA+ Datasheet - Page 6

• Manufacturer Part Number: MAX9022ASA+
• Description: IC COMPARATOR DUAL 8-SOIC
• Manufacturer: Maxim Integrated Products
• Type: General Purposer

Specifications of MAX9022ASA+

• Number Of Elements: 2
• Output Type: CMOS, Rail-to-Rail, TTL
• Voltage - Supply: 2.5 V ~ 5.5 V, ±1.25 V ~ 2.75 V
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Number Of Channels: 2 Channels
• Product: Digital Comparators
• Offset Voltage (max): +/- 8 mV
• Input Bias Current (max): 80 nA
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Supply Current (max): 5 uA
• Maximum Power Dissipation: 471 mW
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2) The hysteresis band will be:
3) In this example, let V
4) Select R2. In this example, we will choose 1kΩ.
5) Select V
6) Solve for R1.
The above-described design procedure assumes rail-
to-rail output swing. If the output is significantly loaded,
the results should be corrected.
Micropower, Ultra-Small, Single/Dual/Quad,
Single-Supply Comparators
Figure 1. Additional Hysteresis
6
and
where R1 ≈ 100kΩ, V
V
V
_______________________________________________________________________________________
REF
IN
V
HYS
R2
0.050V = 5(1000Ω/(R1 + 1000Ω)) V
HYS
V
V
TH
TL
= V
V
. In this example, we will choose 50mV.
= 2.5V + 2.5V(R2 / (R1 + R2))
HYS
= 2.5V[(1 - (R2 / (R1 + R2))]
TH
R1
IN+
IN-
= V
- V
TL
DD
DD
TH
= V
(R2 / (R1 + R2))
= 5V and V
= 2.525V, and V
DD
V
V
V
DD
DD
SS
(R2 / (R1 + R2))
MAX9021
REF
OUT
= 2.5V.
TL
= 2.475V.
Use 100nF bypass as a starting point. Minimize signal
trace lengths to reduce stray capacitance. Minimize the
capacitive coupling between IN- and OUT. For slow-
moving input signals (rise time > 1ms), use a 1nF
capacitor between IN+ and IN-.
Digital data is often embedded into a bandwidth and
amplitude-limited analog path. Recovering the data can
be difficult. Figure 2 compares the input signal to a
time-averaged version of itself. This self-biases the
threshold to the average input voltage for optimal noise
margin. Even severe phase distortion is eliminated from
the digital output signal. Be sure to choose R1 and C1
so that:
where f
digital data stream.
Figure 2. Time Averaging of the Input Signal for Data Recovery
V
IN
CAR
10kΩ
0.1µF
is the fundamental carrier frequency of the
f
CAR
Board Layout and Bypassing
IN+
IN-
Biasing for Data Recovery
>> 1 / (2
V
π
V
DD
SS
R1C1)
V
DD
MAX9021
OUT