DS24B33 Maxim, DS24B33 Datasheet - Page 3

• Manufacturer Part Number: DS24B33
• Description: The DS24B33 is a 4096-bit, 1-Wire® EEPROM organized as 16 memory pages of 256 bits each
• Manufacturer: Maxim

ELECTRICAL CHARACTERISTICS (continued)
(T
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10: Voltage above which, during a rising edge on IO, a logic 1 is detected.
Note 11: After V
Note 12: The I-V characteristic is linear for voltages less than +1V.
Note 13: Applies to a single DS24B33 attached to a 1-Wire line.
Note 14: Defines maximum possible bit rate. Equal to 1/(t
Note 15: Interval after t
Note 16: ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from V
Note 17: δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from V
Note 18: Current drawn from IO during the EEPROM programming interval. The pullup circuit on IO should be such that during the
Note 19: The t
IO PIN: 1-Wire WRITE
Write-Zero Low Time
(Notes 2, 16)
Write-One Low Time
(Notes 2, 16)
IO PIN: 1-Wire READ
Read Low Time
(Notes 2, 17)
Read Sample Time
(Notes 2, 17)
EEPROM
Programming Current
Programming Time
Write/Erase Cycles (Endurance)
(Notes 20, 21)
Data Retention (Notes 22, 23, 24)
A
= -40°C to +85°C.) (Note 1)
PARAMETER
Not all parameters are tested at all temperatures.
System requirement.
When operating near the minimum operating voltage (2.8V), a falling edge slew rate of 15V/µs or faster is recommended.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system, 1-Wire recovery times,
and current requirements during EEPROM programming. The specified value here applies to systems with only one
device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found
in the DS2482-x00 or DS2480B may be required.
Capacitance on the data pin could be 2500pF when V
line, then 15µs after V
Guaranteed by design, characterization, and/or simulation only. Not production tested.
V
capacitive loading on IO. Lower V
V
Voltage below which, during a falling edge on IO, a logic 0 is detected.
The voltage on IO must be less than or equal to V
Minimum limit is t
maximum duration for the master to pull the line low is t
threshold of the bus master. The actual maximum duration for the master to pull the line low is t
programming interval, the voltage at IO is greater than or equal to V
a low-impedance bypass of R
pad sequence. The interval ends once the device’s self-timed EEPROM programming cycle is complete and the current
drawn by the device has returned from I
TL
TL
, V
, V
PROG
TH
TH
TH
, and V
, and V
is crossed during a rising edge on IO, the voltage on IO must drop by at least V
_______________________________________________________________________________________
interval begins after the trailing rising edge on IO for the last time slot of the E/S byte for a valid copy scratch-
RSTL
HY
HY
PDHMAX
.
are a function of the internal supply voltage, which is a function of V
during which a bus master is guaranteed to sample a logic 0 on IO if there is a DS24B33 present.
PUP
; maximum limit is t
has been applied, the parasite capacitance does not affect normal communications.
SYMBOL
I
t
PROG
PROG
t
t
t
N
MSR
t
PUP
W0L
W1L
t
DR
RL
CY
, which can be activated during programming, may need to be added.
PUP
, higher R
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
(Note 18)
(Note 19)
At +25°C
At +85°C (worst case)
At +85°C (worst case)
PROG
PDHMIN
to I
PUP
W0LMIN
L
ILMAX
.
, shorter t
+ t
PUP
CONDITIONS
PDLMIN
W1LMAX
at all times while the master is driving IO to a logic 0 level.
+ t
is first applied. If a 2.2kΩ resistor is used to pull up the data
RECMIN
REC
.
+ t
, and heavier capacitive loading all lead to lower values of
).
F
1-Wire 4Kb EEPROM
PUPMIN
- ε and t
. If V
W0LMAX
PUP
in the system is close to V
+ t
200,000
t
t
50,000
RL
RL
PUP
MIN
F
60
40
6
5
1
5
1
- ε, respectively.
+
+
HY
, R
to be detected as logic 0.
PUP
RLMAX
TYP
, 1-Wire timing, and
IL
IL
+ t
to V
to the input high
F
15 -
MAX
.
2 -
TH
120
16
15
15
2
2
2
5
. The actual
PUPMIN
UNITS
Years
mA
ms
μs
μs
μs
μs
—
, then
3