DS1307 Maxim, DS1307 Datasheet - Page 8

• Manufacturer Part Number: DS1307
• Description: The DS1307 serial real-time clock (RTC) is a low-power, full binary-coded decimal (BCD) clock/calendar plus 56 bytes of NV SRAM
• Manufacturer: Maxim

CLOCK AND CALENDAR
The time and calendar information is obtained by reading the appropriate register bytes. Table 2 shows the RTC
registers. The time and calendar are set or initialized by writing the appropriate register bytes. The contents of the
time and calendar registers are in the BCD format. The day-of-week register increments at midnight. Values that
correspond to the day of week are user-defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals
Monday, and so on.) Illogical time and date entries result in undefined operation. Bit 7 of Register 0 is the clock halt
(CH) bit. When this bit is set to 1, the oscillator is disabled. When cleared to 0, the oscillator is enabled. On first
application of power to the device the time and date registers are typically reset to 01/01/00 01 00:00:00
(MM/DD/YY DOW HH:MM:SS). The CH bit in the seconds register will be set to a 1. The clock can be halted
whenever the timekeeping functions are not required, which minimizes current (I
The DS1307 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12-hour or
24-hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with
logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20 to 23 hours). The hours value must be
re-entered whenever the 12/24-hour mode bit is changed.
When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the
internal registers update. When reading the time and date registers, the user buffers are synchronized to the
internal registers on any I
continues to run. This eliminates the need to re-read the registers in case the internal registers update during a
read. The divider chain is reset whenever the seconds register is written. Write transfers occur on the I
acknowledge from the DS1307. Once the divider chain is reset, to avoid rollover issues, the remaining time and
date registers must be written within one second.
Table 2. Timekeeper Registers
0 = Always reads back as 0.
ADDRESS
08h–3Fh
00h
01h
02h
03h
04h
05h
06h
07h
BIT 7
OUT
CH
0
0
0
0
0
BIT 6
2
12
24
0
0
0
0
C START. The time information is read from these secondary registers while the clock
10 Year
10 Seconds
10 Minutes
BIT 5
Hour
PM/
AM
10
0
0
0
10 Date
SQWE
Month
BIT 4
Hour
10
10
0
8 of 14
BIT 3
0
0
BIT 2
0
Seconds
Minutes
Month
Hours
Date
Year
DS1307 64 x 8, Serial, I
BIT 1
DAY
RS1
BATDR
BIT 0
RS0
).
FUNCTION
Seconds
Minutes
Control
Month
56 x 8
Hours
RAM
Date
Year
Day
2
C Real-Time Clock
00h–FFh
+AM/PM
RANGE
00–59
00–59
00–23
01–07
01–31
01–12
00–99
1–12
—
2
C