71M6511 Maxim, 71M6511 Datasheet - Page 34

• Manufacturer Part Number: 71M6511
• Description: The 71M6511 and 71M6511H are highly integrated SoCs with an MPU core, RTC, flash, and LCD driver
• Manufacturer: Maxim

Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in Table 46:
Each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit in
the special function register IP0 and one in IP1. If requests of the same priority level are received simultaneously, an internal
polling sequence as per Table 50 determines which request is serviced first.
IEN enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own flag bit that is set by
the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5). XFER_BUSY and RTC_1SEC,
which are OR-ed together, have their own enable and flag bits in addition to the interrupt 6 enable and flag bits (see Table 45),
and these interrupts must be cleared by the MPU software.
An overview of the interrupt structure is given in Figure 7.
Interrupt Priority 0 Register (IP0)
Interrupt Priority 1 Register (IP1)
Page: 34 of 98
Group
IP1.x
0
1
2
3
4
5
A Maxim Integrated Products Brand
MSB
MSB
Serial channel 0 interrupt
External interrupt 0
External interrupt 1
IP0.x
Timer 0 interrupt
Timer 1 interrupt
--
-
-
Priority Level
WDTS
Note: WDTS is not used for interrupt controls
-
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0
0
1
1
IP0.5
IP1.5
Table 46: Priority Level Groups
Serial channel 1 interrupt
Table 47: The IP0 Register:
Table 48: The IP1 Register:
Table 49: Priority Levels
IP0.4
IP1.4
0
1
0
1
-
-
-
-
-
IP0.3
IP1.3
Single-Phase Energy Meter IC
Level0 (lowest)
Level1
Level2
Level3 (highest)
IP0.2
IP1.2
71M6511/71M6511H
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
DATA SHEET
IP0.1
IP1.1
LSB
LSB
IP0.0
IP1.0
NOVEMBER 2010
V2.7