71M6511 Maxim, 71M6511 Datasheet - Page 55

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71M6511

Manufacturer Part Number
71M6511
Description
The 71M6511 and 71M6511H are highly integrated SoCs with an MPU core, RTC, flash, and LCD driver
Manufacturer
Maxim
Datasheet

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XFER_BUSY interrupt. After these first two cycles, CHOP_EN returns to 11 (automatic toggle). The value of CHOP_EN, when
set after the XFER_BUSY interrupt, is in force for the entire following multiplexer cycle.
When using this sequence, the alternate multiplexer cycle is toggled between positive and reversed connection resulting in
accurate temperature measurement.
An example for proper application of the CHOP_EN bits can be found in the Demo Code shipped with the 6511 and 6511
Demo Kits. Firmware implementations should closely follow this example.
Internal/External Pulse Generation and Pulse Counting
The CE is the source for pulses. It can generate pulses directly based on the voltage and current inputs and the configured
pulse generation parameters. This is called “internal pulse generation”, and applies when the CE RAM register EXT_PULSE
(address 0x37) equals 0. Alternatively, the CE can be configured to generate pulses based on registers that are controlled by
the MPU (“external pulse generation”), i.e. when the register EXT_PULSE equals 15. In the case of external pulse generation,
the MPU writes values to the CE registers APULSEW (0x26) and APULSER (0x27).
The pulse rate, usually inversely expressed as “Kh” (and measured in Wh per pulse), is determined by the CE RAM registers
WRATE, PULSE_SLOW, PULSE_FAST, In_8, as well as by the sensor scaling VMAX and IMAX per the equation:
where
Page: 55 of 98
01
alt. MUX
Positive Positive
cycle
CHOP_EN
A Maxim Integrated Products Brand
XFER_BUSY interrupt
In_8 is the gain factor (1 or 8) controlled by the CE variable In_SHUNT,
X is the pulse gain factor controlled by the CE variables PULSE_SLOW and PULSE_FAST
N
CE_BUSY interrupt
ACC
11
Accumulation Interval m
cycle 2
MUX
MUX_ALT
Chop Polarity
is the accumulation count (PRE_SAMPS * SUM_CYCLES)
(11)
cycle 3
versed
MUX
Figure 23: Sequence with Alternate Multiplexer Cycles and Controlled Chopping
re-
(11)
(11)
Positive
cycle n
MUX
Kh
© 2005–2010 Teridian Semiconductor Corporation
10
alt. MUX
versed
=
cycle
re-
In
VMAX
Accumulation Interval m+1
_
11
8
versed
cycle 2
MUX
re-
WRATE
IMAX
(11)
Positive
cycle 3
MUX
N
(11)
47
ACC
Single-Phase Energy Meter IC
.
1132
(11)
X
cycle n
versed
MUX
re-
[
Wh
71M6511/71M6511H
/
Positive Positive
01
alt. MUX
cycle
pulse
DATA SHEET
Accumulation Interval m+2
11
]
cycle 2
MUX
(11)
versed
cycle 3
MUX
re-
(11)
NOVEMBER 2010
(11)
cycle n
Positive
MUX
V2.7

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